Commit 97d9a4e9 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2020-02-20' of...

Merge tag 'drm-intel-fixes-2020-02-20' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v5.6-rc3:
- Workaround missing Display Stream Compression (DSC) state readout by
  forcing modeset when its enabled at probe
- Fix EHL port clock voltage level requirements
- Fix queuing retire workers on the virtual engine
- Fix use of partially initialized waiters
- Stop using drm_pci_alloc/drm_pci/free
- Fix rewind of RING_TAIL by forcing a context reload
- Fix locking on resetting ring->head
- Propagate our bug filing URL change to stable kernels

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87y2sxtsrd.fsf@intel.com
parents c1368b34 15de9cb5
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+1 −1
Original line number Diff line number Diff line
@@ -8392,7 +8392,7 @@ M: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
M:	Rodrigo Vivi <rodrigo.vivi@intel.com>
L:	intel-gfx@lists.freedesktop.org
W:	https://01.org/linuxgraphics/
B:	https://01.org/linuxgraphics/documentation/how-report-bugs
B:	https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs
C:	irc://chat.freenode.net/intel-gfx
Q:	http://patchwork.freedesktop.org/project/intel-gfx/
T:	git git://anongit.freedesktop.org/drm-intel
+2 −3
Original line number Diff line number Diff line
@@ -75,9 +75,8 @@ config DRM_I915_CAPTURE_ERROR
	help
	  This option enables capturing the GPU state when a hang is detected.
	  This information is vital for triaging hangs and assists in debugging.
	  Please report any hang to
	    https://bugs.freedesktop.org/enter_bug.cgi?product=DRI
	  for triaging.
	  Please report any hang for triaging according to:
	    https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs

	  If in doubt, say "Y".

+3 −1
Original line number Diff line number Diff line
@@ -4251,7 +4251,9 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
					 struct intel_crtc_state *crtc_state)
{
	if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
	if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
		crtc_state->min_voltage_level = 3;
	else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
		crtc_state->min_voltage_level = 1;
	else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
		crtc_state->min_voltage_level = 2;
+19 −1
Original line number Diff line number Diff line
@@ -11087,7 +11087,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
	u32 base;
	if (INTEL_INFO(dev_priv)->display.cursor_needs_physical)
		base = obj->phys_handle->busaddr;
		base = sg_dma_address(obj->mm.pages->sgl);
	else
		base = intel_plane_ggtt_offset(plane_state);
@@ -17433,6 +17433,24 @@ retry:
			 * have readout for pipe gamma enable.
			 */
			crtc_state->uapi.color_mgmt_changed = true;
			/*
			 * FIXME hack to force full modeset when DSC is being
			 * used.
			 *
			 * As long as we do not have full state readout and
			 * config comparison of crtc_state->dsc, we have no way
			 * to ensure reliable fastset. Remove once we have
			 * readout for DSC.
			 */
			if (crtc_state->dsc.compression_enable) {
				ret = drm_atomic_add_affected_connectors(state,
									 &crtc->base);
				if (ret)
					goto out;
				crtc_state->uapi.mode_changed = true;
				drm_dbg_kms(dev, "Force full modeset for DSC\n");
			}
		}
	}
+16 −0
Original line number Diff line number Diff line
@@ -565,6 +565,22 @@ static int __context_set_persistence(struct i915_gem_context *ctx, bool state)
		if (!(ctx->i915->caps.scheduler & I915_SCHEDULER_CAP_PREEMPTION))
			return -ENODEV;

		/*
		 * If the cancel fails, we then need to reset, cleanly!
		 *
		 * If the per-engine reset fails, all hope is lost! We resort
		 * to a full GPU reset in that unlikely case, but realistically
		 * if the engine could not reset, the full reset does not fare
		 * much better. The damage has been done.
		 *
		 * However, if we cannot reset an engine by itself, we cannot
		 * cleanup a hanging persistent context without causing
		 * colateral damage, and we should not pretend we can by
		 * exposing the interface.
		 */
		if (!intel_has_reset_engine(&ctx->i915->gt))
			return -ENODEV;

		i915_gem_context_clear_persistence(ctx);
	}

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