Commit 97b9c3e1 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm 

* 'fixes' of master.kernel.org:/home/rmk/linux-2.6-arm:
  ARM: 6745/1: kprobes insn decoding fix
  ARM: tlb: move noMMU tlb_flush() to asm/tlb.h
  ARM: tlb: delay page freeing for SMP and ARMv7 CPUs
  ARM: Keep exit text/data around for SMP_ON_UP
  ARM: Ensure predictable endian state on signal handler entry
  ARM: 6740/1: Place correctly notes section in the linker script
  ARM: 6700/1: SPEAr: Correct SOC config base address for spear320
  ARM: 6722/1: SPEAr: sp810: switch to slow mode before reset
  ARM: 6712/1: SPEAr: replace readl(), writel() with relaxed versions in uncompress.h
  ARM: 6720/1: SPEAr: Append UL to VMALLOC_END
  ARM: 6676/1: Correct the cpu_architecture() function for ARMv7
  ARM: 6739/1: update .gitignore for boot/compressed
  ARM: 6743/1: errata: interrupted ICALLUIS may prevent completion of broadcasted operation
  ARM: 6742/1: pmu: avoid setting IRQ affinity on UP systems
  ARM: 6741/1: errata: pl310 cache sync operation may be faulty
parents f85cca6b 5a5af730

arch/arm/Kconfig

+25 −0
Original line number Diff line number Diff line
@@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622 
	  visible impact on the overall performance or power consumption of the

	  processor.



config ARM_ERRATA_751472

	bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"

	depends on CPU_V7 && SMP

	help

	  This option enables the workaround for the 751472 Cortex-A9 (prior

	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the

	  completion of a following broadcasted operation if the second

	  operation is received by a CPU before the ICIALLUIS has completed,

	  potentially leading to corrupted entries in the cache or TLB.



config ARM_ERRATA_753970

	bool "ARM errata: cache sync operation may be faulty"

	depends on CACHE_PL310

	help

	  This option enables the workaround for the 753970 PL310 (r3p0) erratum.



	  Under some condition the effect of cache sync operation on

	  the store buffer still remains when the operation completes.

	  This means that the store buffer is always asked to drain and

	  this prevents it from merging any further writes. The workaround

	  is to replace the normal offset of cache sync operation (0x730)

	  by another offset targeting an unmapped PL310 register 0x740.

	  This has the same effect as the cache sync operation: store buffer

	  drain and waiting for all buffers empty.



endmenu



source "arch/arm/common/Kconfig"

arch/arm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y) 
LDFLAGS_vmlinux	+= --be8

endif



OBJCOPYFLAGS	:=-O binary -R .note -R .note.gnu.build-id -R .comment -S

OBJCOPYFLAGS	:=-O binary -R .comment -S

GZFLAGS		:=-9

#KBUILD_CFLAGS	+=-pipe

# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:

arch/arm/boot/compressed/.gitignore

+5 −1
Original line number Diff line number Diff line 
font.c

piggy.gz

lib1funcs.S

piggy.gzip

piggy.lzo

piggy.lzma

vmlinux

vmlinux.lds

arch/arm/include/asm/hardware/cache-l2x0.h

+1 −0
Original line number Diff line number Diff line
@@ -36,6 +36,7 @@ 
#define L2X0_RAW_INTR_STAT		0x21C

#define L2X0_INTR_CLEAR			0x220

#define L2X0_CACHE_SYNC			0x730

#define L2X0_DUMMY_REG			0x740

#define L2X0_INV_LINE_PA		0x770

#define L2X0_INV_WAY			0x77C

#define L2X0_CLEAN_LINE_PA		0x7B0

arch/arm/include/asm/hardware/sp810.h

+3 −0
Original line number Diff line number Diff line
@@ -58,6 +58,9 @@ 


static inline void sysctl_soft_reset(void __iomem *base)

{

	/* switch to slow mode */

	writel(0x2, base + SCCTRL);



	/* writing any value to SCSYSSTAT reg will reset system */

	writel(0, base + SCSYSSTAT);

}

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