Commit 97b2a6a1 authored by John Harrison's avatar John Harrison Committed by Daniel Vetter
Browse files

drm/i915: Replace last_[rwf]_seqno with last_[rwf]_req 



The object structure contains the last read, write and fenced seqno values for
use in syncrhonisation operations. These have now been replaced with their
request structure counterparts.

Note that to ensure that objects do not end up with dangling pointers, the
assignments of last_*_req include reference count updates. Thus a request cannot
be freed if an object is still hanging on to it for any reason.

v2: Corrected 'last_rendering_' to 'last_read_' in a number of comments that did
not get updated when 'last_rendering_seqno' became 'last_read|write_seqno'
several millenia ago.

For: VIZ-4377
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Reviewed-by: default avatarThomas Daniel <Thomas.Daniel@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent b793a00a

drivers/gpu/drm/i915/i915_debugfs.c

+3 −3
Original line number Diff line number Diff line
@@ -131,9 +131,9 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) 
		   obj->base.size / 1024,

		   obj->base.read_domains,

		   obj->base.write_domain,

		   obj->last_read_seqno,

		   obj->last_write_seqno,

		   obj->last_fenced_seqno,

		   i915_gem_request_get_seqno(obj->last_read_req),

		   i915_gem_request_get_seqno(obj->last_write_req),

		   i915_gem_request_get_seqno(obj->last_fenced_req),

		   i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),

		   obj->dirty ? " dirty" : "",

		   obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");

drivers/gpu/drm/i915/i915_drv.h

+7 −6
Original line number Diff line number Diff line
@@ -1944,10 +1944,10 @@ struct drm_i915_gem_object { 
	struct intel_engine_cs *ring;



	/** Breadcrumb of last rendering to the buffer. */

	uint32_t last_read_seqno;

	uint32_t last_write_seqno;

	struct drm_i915_gem_request *last_read_req;

	struct drm_i915_gem_request *last_write_req;

	/** Breadcrumb of last fenced GPU access to the buffer. */

	uint32_t last_fenced_seqno;

	struct drm_i915_gem_request *last_fenced_req;



	/** Current tiling stride for the object, if it's tiled. */

	uint32_t stride;
@@ -1986,9 +1986,10 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old, 
 * The request queue allows us to note sequence numbers that have been emitted

 * and may be associated with active buffers to be retired.

 *

 * By keeping this list, we can avoid having to do questionable

 * sequence-number comparisons on buffer last_rendering_seqnos, and associate

 * an emission time with seqnos for tracking how far ahead of the GPU we are.

 * By keeping this list, we can avoid having to do questionable sequence

 * number comparisons on buffer last_read|write_seqno. It also allows an

 * emission time to be associated with the request for tracking how far ahead

 * of the GPU the submission is.

 */

struct drm_i915_gem_request {

	struct kref ref;

drivers/gpu/drm/i915/i915_gem.c

+41 −30
Original line number Diff line number Diff line
@@ -1346,11 +1346,11 @@ i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) 
	/* Manually manage the write flush as we may have not yet

	 * retired the buffer.

	 *

	 * Note that the last_write_seqno is always the earlier of

	 * the two (read/write) seqno, so if we haved successfully waited,

	 * Note that the last_write_req is always the earlier of

	 * the two (read/write) requests, so if we haved successfully waited,

	 * we know we have passed the last write.

	 */

	obj->last_write_seqno = 0;

	i915_gem_request_assign(&obj->last_write_req, NULL);



	return 0;

}
@@ -1363,14 +1363,18 @@ static __must_check int 
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,

			       bool readonly)

{

	struct drm_i915_gem_request *req;

	struct intel_engine_cs *ring = obj->ring;

	u32 seqno;

	int ret;



	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;

	if (seqno == 0)

	req = readonly ? obj->last_write_req : obj->last_read_req;

	if (!req)

		return 0;



	seqno = i915_gem_request_get_seqno(req);

	WARN_ON(seqno == 0);



	ret = i915_wait_seqno(ring, seqno);

	if (ret)

		return ret;
@@ -1386,6 +1390,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, 
					    struct drm_i915_file_private *file_priv,

					    bool readonly)

{

	struct drm_i915_gem_request *req;

	struct drm_device *dev = obj->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *ring = obj->ring;
@@ -1396,10 +1401,13 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, 
	BUG_ON(!mutex_is_locked(&dev->struct_mutex));

	BUG_ON(!dev_priv->mm.interruptible);



	seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;

	if (seqno == 0)

	req = readonly ? obj->last_write_req : obj->last_read_req;

	if (!req)

		return 0;



	seqno = i915_gem_request_get_seqno(req);

	WARN_ON(seqno == 0);



	ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);

	if (ret)

		return ret;
@@ -2257,12 +2265,12 @@ static void 
i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,

			       struct intel_engine_cs *ring)

{

	u32 seqno = intel_ring_get_seqno(ring);

	struct drm_i915_gem_request *req = intel_ring_get_request(ring);



	BUG_ON(ring == NULL);

	if (obj->ring != ring && obj->last_write_seqno) {

		/* Keep the seqno relative to the current ring */

		obj->last_write_seqno = seqno;

	if (obj->ring != ring && obj->last_write_req) {

		/* Keep the request relative to the current ring */

		i915_gem_request_assign(&obj->last_write_req, req);

	}

	obj->ring = ring;
@@ -2274,7 +2282,7 @@ i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 


	list_move_tail(&obj->ring_list, &ring->active_list);



	obj->last_read_seqno = seqno;

	i915_gem_request_assign(&obj->last_read_req, req);

}



void i915_vma_move_to_active(struct i915_vma *vma,
@@ -2305,11 +2313,11 @@ i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) 
	list_del_init(&obj->ring_list);

	obj->ring = NULL;



	obj->last_read_seqno = 0;

	obj->last_write_seqno = 0;

	i915_gem_request_assign(&obj->last_read_req, NULL);

	i915_gem_request_assign(&obj->last_write_req, NULL);

	obj->base.write_domain = 0;



	obj->last_fenced_seqno = 0;

	i915_gem_request_assign(&obj->last_fenced_req, NULL);



	obj->active = 0;

	drm_gem_object_unreference(&obj->base);
@@ -2326,7 +2334,7 @@ i915_gem_object_retire(struct drm_i915_gem_object *obj) 
		return;



	if (i915_seqno_passed(ring->get_seqno(ring, true),

			      obj->last_read_seqno))

			      i915_gem_request_get_seqno(obj->last_read_req)))

		i915_gem_object_move_to_inactive(obj);

}
@@ -2753,7 +2761,8 @@ i915_gem_retire_requests_ring(struct intel_engine_cs *ring) 
				      struct drm_i915_gem_object,

				      ring_list);



		if (!i915_seqno_passed(seqno, obj->last_read_seqno))

		if (!i915_seqno_passed(seqno,

			     i915_gem_request_get_seqno(obj->last_read_req)))

			break;



		i915_gem_object_move_to_inactive(obj);
@@ -2872,7 +2881,8 @@ i915_gem_object_flush_active(struct drm_i915_gem_object *obj) 
	int ret;



	if (obj->active) {

		ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);

		ret = i915_gem_check_olr(obj->ring,

			     i915_gem_request_get_seqno(obj->last_read_req));

		if (ret)

			return ret;
@@ -2933,14 +2943,13 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 
	if (ret)

		goto out;



	if (obj->active) {

		seqno = obj->last_read_seqno;

		ring = obj->ring;

	}



	if (seqno == 0)

	if (!obj->active || !obj->last_read_req)

		goto out;



	seqno = i915_gem_request_get_seqno(obj->last_read_req);

	WARN_ON(seqno == 0);

	ring = obj->ring;



	/* Do this after OLR check to make sure we make forward progress polling

	 * on this IOCTL with a timeout <=0 (like busy ioctl)

	 */
@@ -2990,7 +2999,7 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj, 


	idx = intel_ring_sync_index(from, to);



	seqno = obj->last_read_seqno;

	seqno = i915_gem_request_get_seqno(obj->last_read_req);

	/* Optimization: Avoid semaphore sync when we are sure we already

	 * waited for an object with higher seqno */

	if (seqno <= from->semaphore.sync_seqno[idx])
@@ -3003,11 +3012,12 @@ i915_gem_object_sync(struct drm_i915_gem_object *obj, 
	trace_i915_gem_ring_sync_to(from, to, seqno);

	ret = to->semaphore.sync_to(to, from, seqno);

	if (!ret)

		/* We use last_read_seqno because sync_to()

		/* We use last_read_req because sync_to()

		 * might have just caused seqno wrap under

		 * the radar.

		 */

		from->semaphore.sync_seqno[idx] = obj->last_read_seqno;

		from->semaphore.sync_seqno[idx] =

				i915_gem_request_get_seqno(obj->last_read_req);



	return ret;

}
@@ -3321,12 +3331,13 @@ static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, 
static int

i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)

{

	if (obj->last_fenced_seqno) {

		int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);

	if (obj->last_fenced_req) {

		int ret = i915_wait_seqno(obj->ring,

			   i915_gem_request_get_seqno(obj->last_fenced_req));

		if (ret)

			return ret;



		obj->last_fenced_seqno = 0;

		i915_gem_request_assign(&obj->last_fenced_req, NULL);

	}



	return 0;

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+3 −3
Original line number Diff line number Diff line
@@ -946,7 +946,7 @@ void 
i915_gem_execbuffer_move_to_active(struct list_head *vmas,

				   struct intel_engine_cs *ring)

{

	u32 seqno = intel_ring_get_seqno(ring);

	struct drm_i915_gem_request *req = intel_ring_get_request(ring);

	struct i915_vma *vma;



	list_for_each_entry(vma, vmas, exec_list) {
@@ -963,7 +963,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas, 
		i915_vma_move_to_active(vma, ring);

		if (obj->base.write_domain) {

			obj->dirty = 1;

			obj->last_write_seqno = seqno;

			i915_gem_request_assign(&obj->last_write_req, req);



			intel_fb_obj_invalidate(obj, ring);
@@ -971,7 +971,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas, 
			obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;

		}

		if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {

			obj->last_fenced_seqno = seqno;

			i915_gem_request_assign(&obj->last_fenced_req, req);

			if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {

				struct drm_i915_private *dev_priv = to_i915(ring->dev);

				list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,

drivers/gpu/drm/i915/i915_gem_gtt.h

+2 −2
Original line number Diff line number Diff line
@@ -181,7 +181,7 @@ struct i915_address_space { 
	 * List of objects currently involved in rendering.

	 *

	 * Includes buffers having the contents of their GPU caches

	 * flushed, not necessarily primitives.  last_rendering_seqno

	 * flushed, not necessarily primitives. last_read_req

	 * represents when the rendering involved will be completed.

	 *

	 * A reference is held on the buffer while on this list.
@@ -192,7 +192,7 @@ struct i915_address_space { 
	 * LRU list of objects which are not in the ringbuffer and

	 * are ready to unbind, but are still in the GTT.

	 *

	 * last_rendering_seqno is 0 while an object is in this list.

	 * last_read_req is NULL while an object is in this list.

	 *

	 * A reference is not held on the buffer while on this list,

	 * as merely being GTT-bound shouldn't prevent its being

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