Commit 9774a96f authored by Babu Moger's avatar Babu Moger Committed by Borislav Petkov
Browse files

x86/umip: Make the comments vendor-agnostic 



AMD 2nd generation EPYC processors also support the UMIP feature. Make
the comments vendor-agnostic.

Signed-off-by: default avatarBabu Moger <babu.moger@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "x86@kernel.org" <x86@kernel.org>
Link: https://lkml.kernel.org/r/157298913784.17462.12654728938970637305.stgit@naples-babu.amd.com
parent b971880f

arch/x86/kernel/umip.c

+6 −6
Original line number Diff line number Diff line 
/*

 * umip.c Emulation for instruction protected by the Intel User-Mode

 * Instruction Prevention feature

 * umip.c Emulation for instruction protected by the User-Mode Instruction

 * Prevention feature

 *

 * Copyright (c) 2017, Intel Corporation.

 * Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
@@ -18,10 +18,10 @@ 


/** DOC: Emulation for User-Mode Instruction Prevention (UMIP)

 *

 * The feature User-Mode Instruction Prevention present in recent Intel

 * processor prevents a group of instructions (SGDT, SIDT, SLDT, SMSW and STR)

 * from being executed with CPL > 0. Otherwise, a general protection fault is

 * issued.

 * User-Mode Instruction Prevention is a security feature present in recent

 * x86 processors that, when enabled, prevents a group of instructions (SGDT,

 * SIDT, SLDT, SMSW and STR) from being run in user mode by issuing a general

 * protection fault if the instruction is executed with CPL > 0.

 *

 * Rather than relaying to the user space the general protection fault caused by

 * the UMIP-protected instructions (in the form of a SIGSEGV signal), it can be

CRA Git | Maintained and supported by SUSTech CRA and CCSE