drm/i915/gvt: add write handler for mmio mbctl (975629c3) · Commits · 戴 / test

Guest will write mmio mbctl which need a special handler in gvt to clear the bit 4 to inidcate the write operation success. V2: use bit definition macro to make code readable. Signed-off-by:

Pei Zhang <pei.zhang@intel.com> Signed-off-by:

Zhenyu Wang <zhenyuw@linux.intel.com>

drivers/gpu/drm/i915/gvt/handlers.c

+9 −1

Original line number	Diff line number	Diff line
		@@ -970,6 +970,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
		return 0;
		}

		static int mbctl_write(struct intel_vgpu *vgpu, unsigned int offset,
		void *p_data, unsigned int bytes)
		{
		(u32 )p_data &= (~GEN6_MBCTL_ENABLE_BOOT_FETCH);
		write_vreg(vgpu, offset, p_data, bytes);
		return 0;
		}

		static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
		void *p_data, unsigned int bytes)
		{
		@@ -2238,7 +2246,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
		MMIO_D(0x7180, D_ALL);
		MMIO_D(0x7408, D_ALL);
		MMIO_D(0x7c00, D_ALL);
		MMIO_D(GEN6_MBCTL, D_ALL);
		MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);
		MMIO_D(0x911c, D_ALL);
		MMIO_D(0x9120, D_ALL);
		MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);

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