Commit 972a55b6 authored by Qiao Zhou's avatar Qiao Zhou Committed by Mark Brown
Browse files

ASoC: fix pxa-ssp compiling issue under mach-mmp 



pxa-ssp.c uses API like cpu_is_pxa3xx(), cpu_is_pxa2xx(), which is
defined under arch-pxa architecture, and drivers under mach-mmp
can't find it. so just use ssp->type to replace that API.

Signed-off-by: default avatarQiao Zhou <zhouqiao@marvell.com>
Acked-by: default avatarHaojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 60172215

include/linux/pxa2xx_ssp.h

+1 −0
Original line number Diff line number Diff line
@@ -160,6 +160,7 @@ enum pxa_ssp_type { 
	PXA25x_SSP,  /* pxa 210, 250, 255, 26x */

	PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */

	PXA27x_SSP,

	PXA3xx_SSP,

	PXA168_SSP,

	PXA910_SSP,

	CE4100_SSP,

sound/soc/pxa/pxa-ssp.c

+11 −27
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 


#include <mach/hardware.h>

#include <mach/dma.h>

#include <mach/audio.h>



#include "../../arm/pxa2xx-pcm.h"

#include "pxa-ssp.h"
@@ -194,7 +193,7 @@ static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) 
{

	u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);



	if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) {

	if (ssp->type == PXA25x_SSP) {

		sscr0 &= ~0x0000ff00;

		sscr0 |= ((div - 2)/2) << 8; /* 2..512 */

	} else {
@@ -212,7 +211,7 @@ static u32 pxa_ssp_get_scr(struct ssp_device *ssp) 
	u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);

	u32 div;



	if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP)

	if (ssp->type == PXA25x_SSP)

		div = ((sscr0 >> 8) & 0xff) * 2 + 2;

	else

		div = ((sscr0 >> 8) & 0xfff) + 1;
@@ -242,7 +241,7 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 
		break;

	case PXA_SSP_CLK_PLL:

		/* Internal PLL is fixed */

		if (cpu_is_pxa25x())

		if (ssp->type == PXA25x_SSP)

			priv->sysclk = 1843200;

		else

			priv->sysclk = 13000000;
@@ -266,11 +265,11 @@ static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 


	/* The SSP clock must be disabled when changing SSP clock mode

	 * on PXA2xx.  On PXA3xx it must be enabled when doing so. */

	if (!cpu_is_pxa3xx())

	if (ssp->type != PXA3xx_SSP)

		clk_disable(ssp->clk);

	val = pxa_ssp_read_reg(ssp, SSCR0) | sscr0;

	pxa_ssp_write_reg(ssp, SSCR0, val);

	if (!cpu_is_pxa3xx())

	if (ssp->type != PXA3xx_SSP)

		clk_enable(ssp->clk);



	return 0;
@@ -294,24 +293,20 @@ static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, 
	case PXA_SSP_AUDIO_DIV_SCDB:

		val = pxa_ssp_read_reg(ssp, SSACD);

		val &= ~SSACD_SCDB;

#if defined(CONFIG_PXA3xx)

		if (cpu_is_pxa3xx())

		if (ssp->type == PXA3xx_SSP)

			val &= ~SSACD_SCDX8;

#endif

		switch (div) {

		case PXA_SSP_CLK_SCDB_1:

			val |= SSACD_SCDB;

			break;

		case PXA_SSP_CLK_SCDB_4:

			break;

#if defined(CONFIG_PXA3xx)

		case PXA_SSP_CLK_SCDB_8:

			if (cpu_is_pxa3xx())

			if (ssp->type == PXA3xx_SSP)

				val |= SSACD_SCDX8;

			else

				return -EINVAL;

			break;

#endif

		default:

			return -EINVAL;

		}
@@ -337,10 +332,8 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, 
	struct ssp_device *ssp = priv->ssp;

	u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;



#if defined(CONFIG_PXA3xx)

	if (cpu_is_pxa3xx())

	if (ssp->type == PXA3xx_SSP)

		pxa_ssp_write_reg(ssp, SSACDD, 0);

#endif



	switch (freq_out) {

	case 5622000:
@@ -365,11 +358,10 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, 
		break;



	default:

#ifdef CONFIG_PXA3xx

		/* PXA3xx has a clock ditherer which can be used to generate

		 * a wider range of frequencies - calculate a value for it.

		 */

		if (cpu_is_pxa3xx()) {

		if (ssp->type == PXA3xx_SSP) {

			u32 val;

			u64 tmp = 19968;

			tmp *= 1000000;
@@ -386,7 +378,6 @@ static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, int pll_id, 
				val, freq_out);

			break;

		}

#endif



		return -EINVAL;

	}
@@ -590,10 +581,8 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, 
	/* bit size */

	switch (params_format(params)) {

	case SNDRV_PCM_FORMAT_S16_LE:

#ifdef CONFIG_PXA3xx

		if (cpu_is_pxa3xx())

		if (ssp->type == PXA3xx_SSP)

			sscr0 |= SSCR0_FPCKE;

#endif

		sscr0 |= SSCR0_DataSize(16);

		break;

	case SNDRV_PCM_FORMAT_S24_LE:
@@ -618,9 +607,7 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, 
			* trying and failing a lot; some of the registers

			* needed for that mode are only available on PXA3xx.

			*/



#ifdef CONFIG_PXA3xx

			if (!cpu_is_pxa3xx())

			if (ssp->type != PXA3xx_SSP)

				return -EINVAL;



			sspsp |= SSPSP_SFRMWDTH(width * 2);
@@ -628,9 +615,6 @@ static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, 
			sspsp |= SSPSP_EDMYSTOP(3);

			sspsp |= SSPSP_DMYSTOP(3);

			sspsp |= SSPSP_DMYSTRT(1);

#else

			return -EINVAL;

#endif

		} else {

			/* The frame width is the width the LRCLK is

			 * asserted for; the delay is expressed in

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