Commit 972a34e1 authored by Ran Wang's avatar Ran Wang Committed by Greg Kroah-Hartman
Browse files

usb: ehci: fsl: Update register accessing for arm/arm64 platforms 



arm/arm64's io.h doesn't define clrbits32() and clrsetbits_be32(), which
causing compile failure on some Layerscape Platforms (such as LS1021A and
LS2012A which also integrates FSL EHCI controller). So use
ioread32be()/iowrite32be() instead to make it workable on both
powerpc and arm.

Signed-off-by: default avatarRan Wang <ran.wang_1@nxp.com>
Acked-by: default avatarAlan Stern <stern@rowland.harvard.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 02a50b87

drivers/usb/host/ehci-fsl.c

+41 −21
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <linux/platform_device.h>

#include <linux/fsl_devices.h>

#include <linux/of_platform.h>

#include <linux/io.h>



#include "ehci.h"

#include "ehci-fsl.h"
@@ -50,6 +51,7 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) 
	struct resource *res;

	int irq;

	int retval;

	u32 tmp;



	pr_debug("initializing FSL-SOC USB Controller\n");
@@ -114,17 +116,22 @@ static int fsl_ehci_drv_probe(struct platform_device *pdev) 
	}



	/* Enable USB controller, 83xx or 8536 */

	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)

		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,

				CONTROL_REGISTER_W1C_MASK, 0x4);



	if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) {

		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);

		tmp &= ~CONTROL_REGISTER_W1C_MASK;

		tmp |= 0x4;

		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);

	}

	/*

	 * Enable UTMI phy and program PTS field in UTMI mode before asserting

	 * controller reset for USB Controller version 2.5

	 */

	if (pdata->has_fsl_erratum_a007792) {

		clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,

				CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);

		tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL);

		tmp &= ~CONTROL_REGISTER_W1C_MASK;

		tmp |= CTRL_UTMI_PHY_EN;

		iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL);



		writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);

	}
@@ -174,7 +181,7 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
			       enum fsl_usb2_phy_modes phy_mode,

			       unsigned int port_offset)

{

	u32 portsc;

	u32 portsc, tmp;

	struct ehci_hcd *ehci = hcd_to_ehci(hcd);

	void __iomem *non_ehci = hcd->regs;

	struct device *dev = hcd->self.controller;
@@ -192,11 +199,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
	case FSL_USB2_PHY_ULPI:

		if (pdata->have_sysif_regs && pdata->controller_ver) {

			/* controller version 1.6 or above */

			clrbits32(non_ehci + FSL_SOC_USB_CTRL,

				  CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);

			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

					CONTROL_REGISTER_W1C_MASK,

					ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);

			/* turn off UTMI PHY first */

			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);

			tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);

			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);



			/* then turn on ULPI and enable USB controller */

			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);

			tmp &= ~CONTROL_REGISTER_W1C_MASK;

			tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN;

			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);

		}

		portsc |= PORT_PTS_ULPI;

		break;
@@ -210,16 +222,21 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 
	case FSL_USB2_PHY_UTMI_DUAL:

		if (pdata->have_sysif_regs && pdata->controller_ver) {

			/* controller version 1.6 or above */

			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

					CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);

			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);

			tmp &= ~CONTROL_REGISTER_W1C_MASK;

			tmp |= UTMI_PHY_EN;

			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);



			mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to

						become stable - 10ms*/

		}

		/* enable UTMI PHY */

		if (pdata->have_sysif_regs)

			clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

					CONTROL_REGISTER_W1C_MASK,

					CTRL_UTMI_PHY_EN);

		if (pdata->have_sysif_regs) {

			tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);

			tmp &= ~CONTROL_REGISTER_W1C_MASK;

			tmp |= CTRL_UTMI_PHY_EN;

			iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);

		}

		portsc |= PORT_PTS_UTMI;

		break;

	case FSL_USB2_PHY_NONE:
@@ -241,9 +258,12 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 


	ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);



	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)

		clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,

				CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);

	if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) {

		tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL);

		tmp &= ~CONTROL_REGISTER_W1C_MASK;

		tmp |= USB_CTRL_USB_EN;

		iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL);

	}



	return 0;

}

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