Commit 96f59fe2 authored by Thomas Gleixner's avatar Thomas Gleixner Committed by Borislav Petkov
Browse files

x86/tlb: Move cr4_set_bits_and_update_boot() to the usage site 



No point in having this exposed.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Reviewed-by: default avatarAlexandre Chartre <alexandre.chartre@oracle.com>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200421092559.940978251@linutronix.de
parent 69de6c1a

arch/x86/include/asm/tlbflush.h

+0 −14
Original line number Diff line number Diff line
@@ -322,23 +322,9 @@ static inline void cr4_clear_bits(unsigned long mask) 
	local_irq_restore(flags);

}



/*

 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB

 * enable and PPro Global page enable), so that any CPU's that boot

 * up after us can get the correct flags.  This should only be used

 * during boot on the boot cpu.

 */

extern unsigned long mmu_cr4_features;

extern u32 *trampoline_cr4_features;



static inline void cr4_set_bits_and_update_boot(unsigned long mask)

{

	mmu_cr4_features |= mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4_set_bits(mask);

}



extern void initialize_tlbstate_and_flush(void);



#define TLB_FLUSH_ALL	-1UL

arch/x86/mm/init.c

+13 −0
Original line number Diff line number Diff line
@@ -194,6 +194,19 @@ struct map_range { 


static int page_size_mask;



/*

 * Save some of cr4 feature set we're using (e.g.  Pentium 4MB

 * enable and PPro Global page enable), so that any CPU's that boot

 * up after us can get the correct flags. Invoked on the boot CPU.

 */

static inline void cr4_set_bits_and_update_boot(unsigned long mask)

{

	mmu_cr4_features |= mask;

	if (trampoline_cr4_features)

		*trampoline_cr4_features = mmu_cr4_features;

	cr4_set_bits(mask);

}



static void __init probe_page_size_mask(void)

{

	/*

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