Commit 96e5d312 authored by George Cherian's avatar George Cherian Committed by Felipe Balbi
Browse files

usb: dwc3: dwc3-omap: Fix disable IRQ 



In the wrapper the IRQ disable should be done by writing 1's to the
IRQ*_CLR register. Existing code is broken because it instead writes
zeros to IRQ*_SET register.

Fix this by adding functions dwc3_omap_write_irqmisc_clr() and
dwc3_omap_write_irq0_clr() which do the right thing.

Fixes: 72246da4 ("usb: Introduce DesignWare USB3 DRD Driver")
Cc: <stable@vger.kernel.org> # v3.2+
Signed-off-by: default avatarGeorge Cherian <george.cherian@ti.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 1f754ef1

drivers/usb/dwc3/dwc3-omap.c

+28 −2
Original line number Diff line number Diff line
@@ -205,6 +205,18 @@ static void dwc3_omap_write_irq0_set(struct dwc3_omap *omap, u32 value) 
						omap->irq0_offset, value);

}



static void dwc3_omap_write_irqmisc_clr(struct dwc3_omap *omap, u32 value)

{

	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_MISC +

						omap->irqmisc_offset, value);

}



static void dwc3_omap_write_irq0_clr(struct dwc3_omap *omap, u32 value)

{

	dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_CLR_0 -

						omap->irq0_offset, value);

}



static void dwc3_omap_set_mailbox(struct dwc3_omap *omap,

	enum omap_dwc3_vbus_id_status status)

{
@@ -345,9 +357,23 @@ static void dwc3_omap_enable_irqs(struct dwc3_omap *omap) 


static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)

{

	u32			reg;



	/* disable all IRQs */

	dwc3_omap_write_irqmisc_set(omap, 0x00);

	dwc3_omap_write_irq0_set(omap, 0x00);

	reg = USBOTGSS_IRQO_COREIRQ_ST;

	dwc3_omap_write_irq0_clr(omap, reg);



	reg = (USBOTGSS_IRQMISC_OEVT |

			USBOTGSS_IRQMISC_DRVVBUS_RISE |

			USBOTGSS_IRQMISC_CHRGVBUS_RISE |

			USBOTGSS_IRQMISC_DISCHRGVBUS_RISE |

			USBOTGSS_IRQMISC_IDPULLUP_RISE |

			USBOTGSS_IRQMISC_DRVVBUS_FALL |

			USBOTGSS_IRQMISC_CHRGVBUS_FALL |

			USBOTGSS_IRQMISC_DISCHRGVBUS_FALL |

			USBOTGSS_IRQMISC_IDPULLUP_FALL);



	dwc3_omap_write_irqmisc_clr(omap, reg);

}



static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);

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