mtd: rawnand: Reorder the nand_chip->options flags (96d627bd) · Commits · 戴 / test

include/linux/mtd/rawnand.h

+30 −27

Original line number	Diff line number	Diff line
		@@ -118,20 +118,25 @@ enum nand_ecc_algo {
		#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
		#define NAND_ECC_MAXIMIZE BIT(1)

		/*
		* When using software implementation of Hamming, we can specify which byte
		* ordering should be used.
		*/
		#define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)

		/*
		* Option constants for bizarre disfunctionality and real
		* features.
		*/

		/* Buswidth is 16 bit */
		#define NAND_BUSWIDTH_16 BIT(1)

		/*
		* When using software implementation of Hamming, we can specify which byte
		* ordering should be used.
		*/
		#define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)

		/* Chip has cache program function */
		#define NAND_CACHEPRG BIT(3)
		/* Options valid for Samsung large page devices */
		#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG

		/*
		* Chip requires ready check on read (for auto-incremented sequential read).
		* True only for small page devices; large page devices do not support
		@@ -150,6 +155,8 @@ enum nand_ecc_algo {

		/* Device supports subpage reads */
		#define NAND_SUBPAGE_READ BIT(12)
		/* Macros to identify the above */
		#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))

		/*
		* Some MLC NANDs need data scrambling to limit bitflips caused by repeated
		@@ -160,32 +167,12 @@ enum nand_ecc_algo {
		/* Device needs 3rd row address cycle */
		#define NAND_ROW_ADDR_3 BIT(14)

		/* Options valid for Samsung large page devices */
		#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG

		/* Macros to identify the above */
		#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))

		/*
		* There are different places where the manufacturer stores the factory bad
		* block markers.
		*
		* Position within the block: Each of these pages needs to be checked for a
		* bad block marking pattern.
		*/
		#define NAND_BBM_FIRSTPAGE BIT(24)
		#define NAND_BBM_SECONDPAGE BIT(25)
		#define NAND_BBM_LASTPAGE BIT(26)

		/* Position within the OOB data of the page */
		#define NAND_BBM_POS_SMALL 5
		#define NAND_BBM_POS_LARGE 0

		/* Non chip related options */
		/* This option skips the bbt scan during initialization. */
		#define NAND_SKIP_BBTSCAN BIT(16)
		/* Chip may not exist, so silence any errors in scan */
		#define NAND_SCAN_SILENT_NODEV BIT(18)

		/*
		* Autodetect nand buswidth with readid/onfi.
		* This suppose the driver will configure the hardware in 8 bits mode
		@@ -193,6 +180,7 @@ enum nand_ecc_algo {
		* before calling nand_scan_tail.
		*/
		#define NAND_BUSWIDTH_AUTO BIT(19)

		/*
		* This option could be defined by controller drivers to protect against
		* kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
		@@ -222,11 +210,26 @@ enum nand_ecc_algo {
		*/
		#define NAND_KEEP_TIMINGS BIT(23)

		/*
		* There are different places where the manufacturer stores the factory bad
		* block markers.
		*
		* Position within the block: Each of these pages needs to be checked for a
		* bad block marking pattern.
		*/
		#define NAND_BBM_FIRSTPAGE BIT(24)
		#define NAND_BBM_SECONDPAGE BIT(25)
		#define NAND_BBM_LASTPAGE BIT(26)

		/* Cell info constants */
		#define NAND_CI_CHIPNR_MSK 0x03
		#define NAND_CI_CELLTYPE_MSK 0x0C
		#define NAND_CI_CELLTYPE_SHIFT 2

		/* Position within the OOB data of the page */
		#define NAND_BBM_POS_SMALL 5
		#define NAND_BBM_POS_LARGE 0

		/**
		* struct nand_parameters - NAND generic parameters from the parameter page
		* @model: Model name

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