Unverified Commit 968dc5a0 authored by 谢致邦 (XIE Zhibang)'s avatar 谢致邦 (XIE Zhibang) Committed by Paul Burton
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MIPS: Loongson: Set Loongson32 to MIPS32R1 



LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit))
is the CPU core (microarchitecture) of Loongson 1A/1B/1C.

According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the
MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2
instruction set.

In the manual, LS232 implements all of the MIPS32R2 instruction set
except the FPU instructions, and LS232 also implements 5 FPU
instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt,
FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt.

But a bug of the DI instruction has been found during tests, the DI
instruction can not disable interrupts in arch_local_irq_disable() with
CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases.

[paul.burton@mips.com:
  - Remove the _MIPS_ISA redefinition to match the change made for the
    generic MIPSr1 CPUs by commit 344ebf09 ("MIPS: Always use
    -march=<arch>, not -<arch> shortcuts").]

Signed-off-by: default avatar谢致邦 (XIE Zhibang) <Yeking@Red54.com>
Signed-off-by: default avatarPaul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/16155/
Cc: linux-mips@linux-mips.org
Cc: ralf@linux-mips.org
parent 6386889a

arch/mips/Kconfig

+5 −3
Original line number Original line Diff line number Diff line
@@ -1424,7 +1424,8 @@ config CPU_LOONGSON1B 
	select LEDS_GPIO_REGISTER

	select LEDS_GPIO_REGISTER

	help

	help

	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32

	  The Loongson 1B is a 32-bit SoC, which implements the MIPS32

	  release 2 instruction set.

	  Release 1 instruction set and part of the MIPS32 Release 2

	  instruction set.





config CPU_LOONGSON1C

config CPU_LOONGSON1C

	bool "Loongson 1C"

	bool "Loongson 1C"
@@ -1433,7 +1434,8 @@ config CPU_LOONGSON1C 
	select LEDS_GPIO_REGISTER

	select LEDS_GPIO_REGISTER

	help

	help

	  The Loongson 1C is a 32-bit SoC, which implements the MIPS32

	  The Loongson 1C is a 32-bit SoC, which implements the MIPS32

	  release 2 instruction set.

	  Release 1 instruction set and part of the MIPS32 Release 2

	  instruction set.





config CPU_MIPS32_R1

config CPU_MIPS32_R1

	bool "MIPS32 Release 1"

	bool "MIPS32 Release 1"
@@ -1833,7 +1835,7 @@ config CPU_LOONGSON2 
config CPU_LOONGSON1

config CPU_LOONGSON1

	bool

	bool

	select CPU_MIPS32

	select CPU_MIPS32

	select CPU_MIPSR2

	select CPU_MIPSR1

	select CPU_HAS_PREFETCH

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_HIGHMEM

arch/mips/loongson32/Platform

+1 −4
Original line number Original line Diff line number Diff line 
cflags-$(CONFIG_CPU_LOONGSON1)	+= \

cflags-$(CONFIG_CPU_LOONGSON1)		+= -march=mips32 -Wa,--trap

	$(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \

	-Wa,-mips32r2 -Wa,--trap



platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/

platform-$(CONFIG_MACH_LOONGSON32)	+= loongson32/

cflags-$(CONFIG_MACH_LOONGSON32)	+= -I$(srctree)/arch/mips/include/asm/mach-loongson32

cflags-$(CONFIG_MACH_LOONGSON32)	+= -I$(srctree)/arch/mips/include/asm/mach-loongson32

load-$(CONFIG_LOONGSON1_LS1B)		+= 0xffffffff80100000

load-$(CONFIG_LOONGSON1_LS1B)		+= 0xffffffff80100000

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