Commit 96831337 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm DTS changes for 5.7:

 - New support for i.MX6/7 based PICO devices and Toradex i.MX7 based
   Aster boards.
 - Add voltage monitor device node for vf610-zii boards.
 - Improve UART pins macro defines for i.MX6SX SoC and switch related
   boards to use the new names.
 - Use generic node name for devices like GPT, KPP, CCM, WDOG, OCOTP and
   IOMUXC in i.MX DTS files.
 - Switch imx6ul-pico device tree to DRM bindings.
 - Use SPDX-License-Identifier for all Toradex i.MX6/7 based boards.
 - Add proper rgmii PHY description for imx6dl-riotboard and
   imx6q-marsboard.
 - Add capture-subsystem device support for i.MX51.
 - Kill off "simple-panel" compatibles which has never been an accepted
   as an upstream compatible string.
 - Random device addition to various boards.

* tag 'imx-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (55 commits)
  ARM: dts: imx6q-marsboard: properly define rgmii PHY
  ARM: dts: imx6dl-riotboard: properly define rgmii PHY
  ARM: dts: imx51-zii-rdu1: set name prefix for TPA6130A2
  ARM: dts: imx6: RDU2: assign video PLL as input to LDB
  ARM: dts: vf: toradex: SPDX tags and copyright cleanup
  ARM: dts: imx7: toradex: use SPDX-License-Identifier
  ARM: dts: imx6: toradex: use SPDX-License-Identifier
  ARM: dts: imx51: add capture-subsystem device
  ARM: dts: imx: add nvmem property for cpu0
  ARM: dts: imx6qdl: Add imx6qdl-pico support
  ARM: dts: imx6ul-pico: Add support for the dwarf baseboard
  ARM: dts: imx7d-pico: Add support for the nymph baseboard
  ARM: dts: imx7d-pico: Add support for the dwarf baseboard
  ARM: dts: imx23: introduce mmc0_sck_cfg
  ARM: dts: imx25-pinfunc: add config for kpp rows 4 to 7
  ARM: dts: imx: align name for crypto node and child nodes
  ARM: dts: imx6qdl-gw5910: add CC1352 UART
  ARM: dts: imx6qdl-sr-som-ti: indicate powering off wifi is safe
  ARM: dts: imx6: phycore-som: add da9062 gpio support
  ARM: dts: imx6: phycore-som: explicit disable pmic watchdog during suspend
  ...

Link: https://lore.kernel.org/r/20200318051918.32579-4-shawnguo@kernel.org


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 5e4b9a57 2d42fa31
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+14 −0
Original line number Diff line number Diff line
@@ -446,6 +446,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
	imx6dl-nitrogen6x.dtb \
	imx6dl-phytec-mira-rdk-nand.dtb \
	imx6dl-phytec-pbab01.dtb \
	imx6dl-pico-dwarf.dtb \
	imx6dl-pico-hobbit.dtb \
	imx6dl-pico-nymph.dtb \
	imx6dl-pico-pi.dtb \
	imx6dl-rex-basic.dtb \
	imx6dl-riotboard.dtb \
	imx6dl-sabreauto.dtb \
@@ -529,6 +533,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
	imx6q-phytec-mira-rdk-emmc.dtb \
	imx6q-phytec-mira-rdk-nand.dtb \
	imx6q-phytec-pbab01.dtb \
	imx6q-pico-dwarf.dtb \
	imx6q-pico-hobbit.dtb \
	imx6q-pico-nymph.dtb \
	imx6q-pico-pi.dtb \
	imx6q-pistachio.dtb \
	imx6q-rex-pro.dtb \
	imx6q-sabreauto.dtb \
@@ -594,6 +602,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
	imx6ul-kontron-n6310-s-43.dtb \
	imx6ul-liteboard.dtb \
	imx6ul-opos6uldev.dtb \
	imx6ul-pico-dwarf.dtb \
	imx6ul-pico-hobbit.dtb \
	imx6ul-pico-pi.dtb \
	imx6ul-phytec-segin-ff-rdk-nand.dtb \
@@ -610,12 +619,16 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
	imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
	imx7d-cl-som-imx7.dtb \
	imx7d-colibri-aster.dtb \
	imx7d-colibri-emmc-aster.dtb \
	imx7d-colibri-emmc-eval-v3.dtb \
	imx7d-colibri-eval-v3.dtb \
	imx7d-mba7.dtb \
	imx7d-meerkat96.dtb \
	imx7d-nitrogen7.dtb \
	imx7d-pico-dwarf.dtb \
	imx7d-pico-hobbit.dtb \
	imx7d-pico-nymph.dtb \
	imx7d-pico-pi.dtb \
	imx7d-sbc-imx7.dtb \
	imx7d-sdb.dtb \
@@ -623,6 +636,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
	imx7d-sdb-sht11.dtb \
	imx7d-zii-rmu2.dtb \
	imx7d-zii-rpu2.dtb \
	imx7s-colibri-aster.dtb \
	imx7s-colibri-eval-v3.dtb \
	imx7s-mba7.dtb \
	imx7s-warp.dtb
+1 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@
			ssp0: spi@80010000 {
				compatible = "fsl,imx23-mmc";
				pinctrl-names = "default";
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
				pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
				bus-width = <4>;
				broken-cd;
				status = "okay";
+9 −1
Original line number Diff line number Diff line
@@ -267,6 +267,14 @@
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				mmc0_sck_cfg: mmc0-sck-cfg@0 {
					reg = <0>;
					fsl,pinmux-ids = <
						MX23_PAD_SSP1_SCK__SSP1_SCK
					>;
					fsl,pull-up = <MXS_PULL_DISABLE>;
				};

				mmc1_4bit_pins_a: mmc1-4bit@0 {
					reg = <0>;
					fsl,pinmux-ids = <
@@ -422,7 +430,7 @@
				clocks = <&clks 16>;
			};

			dcp@80028000 {
			dcp: crypto@80028000 {
				compatible = "fsl,imx23-dcp";
				reg = <0x80028000 0x2000>;
				interrupts = <53 54>;
+8 −0
Original line number Diff line number Diff line
@@ -82,6 +82,7 @@
#define MX25_PAD_EB0__EB0			0x040 0x258 0x000 0x00 0x000
#define MX25_PAD_EB0__AUD4_TXD			0x040 0x258 0x464 0x04 0x000
#define MX25_PAD_EB0__GPIO_2_12			0x040 0x258 0x000 0x05 0x000
#define MX25_PAD_EB0__CSPI3_SS0			0x040 0x258 0x4bc 0x06 0x000

#define MX25_PAD_EB1__EB1			0x044 0x25c 0x000 0x00 0x000
#define MX25_PAD_EB1__AUD4_RXD			0x044 0x25c 0x460 0x04 0x000
@@ -102,11 +103,13 @@
#define MX25_PAD_CS4__NF_CE1			0x054 0x264 0x000 0x01 0x000
#define MX25_PAD_CS4__UART5_CTS			0x054 0x264 0x000 0x03 0x000
#define MX25_PAD_CS4__GPIO_3_20			0x054 0x264 0x000 0x05 0x000
#define MX25_PAD_CS4__CSPI3_MOSI		0x054 0x264 0x4b8 0x06 0x000

#define MX25_PAD_CS5__CS5			0x058 0x268 0x000 0x00 0x000
#define MX25_PAD_CS5__NF_CE2			0x058 0x268 0x000 0x01 0x000
#define MX25_PAD_CS5__UART5_RTS			0x058 0x268 0x574 0x03 0x000
#define MX25_PAD_CS5__GPIO_3_21			0x058 0x268 0x000 0x05 0x000
#define MX25_PAD_CS5__CSPI3_MISO		0x058 0x268 0x4b4 0x06 0x000

#define MX25_PAD_NF_CE0__NF_CE0			0x05c 0x26c 0x000 0x00 0x000
#define MX25_PAD_NF_CE0__GPIO_3_22		0x05c 0x26c 0x000 0x05 0x000
@@ -114,6 +117,7 @@
#define MX25_PAD_ECB__ECB			0x060 0x270 0x000 0x00 0x000
#define MX25_PAD_ECB__UART5_TXD			0x060 0x270 0x000 0x03 0x000
#define MX25_PAD_ECB__GPIO_3_23			0x060 0x270 0x000 0x05 0x000
#define MX25_PAD_ECB__CSPI3_SCLK		0x060 0x270 0x4ac 0x06 0x000

#define MX25_PAD_LBA__LBA			0x064 0x274 0x000 0x00 0x000
#define MX25_PAD_LBA__UART5_RXD			0x064 0x274 0x578 0x03 0x000
@@ -251,10 +255,12 @@

#define MX25_PAD_LD12__LD12			0x0f8 0x2f0 0x000 0x00 0x000
#define MX25_PAD_LD12__CSPI2_MOSI		0x0f8 0x2f0 0x4a0 0x02 0x000
#define MX25_PAD_LD12__KPP_ROW6			0x0f8 0x2f0 0x544 0x04 0x000
#define MX25_PAD_LD12__FEC_RDATA3		0x0f8 0x2f0 0x510 0x05 0x001

#define MX25_PAD_LD13__LD13			0x0fc 0x2f4 0x000 0x00 0x000
#define MX25_PAD_LD13__CSPI2_MISO		0x0fc 0x2f4 0x49c 0x02 0x000
#define MX25_PAD_LD13__KPP_ROW7			0x0fc 0x2f4 0x548 0x04 0x000
#define MX25_PAD_LD13__FEC_TDATA2		0x0fc 0x2f4 0x000 0x05 0x000

#define MX25_PAD_LD14__LD14			0x100 0x2f8 0x000 0x00 0x000
@@ -512,9 +518,11 @@

#define MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x1d8 0x3d0 0x000 0x00 0x000
#define MX25_PAD_FEC_TX_EN__GPIO_3_9		0x1d8 0x3d0 0x000 0x05 0x000
#define MX25_PAD_FEC_TX_EN__KPP_ROW4		0x1d8 0x3d0 0x53c 0x06 0x000

#define MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x1dc 0x3d4 0x000 0x00 0x000
#define MX25_PAD_FEC_RDATA0__GPIO_3_10		0x1dc 0x3d4 0x000 0x05 0x000
#define MX25_PAD_FEC_RDATA0__KPP_ROW5 		0x1dc 0x3d4 0x540 0x06 0x000

#define MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x1e0 0x3d8 0x000 0x00 0x000
/*
+2 −2
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@
		interrupt-parent = <&asic>;
		ranges;

		aips@43f00000 { /* AIPS1 */
		bus@43f00000 { /* AIPS1 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
@@ -332,7 +332,7 @@
			};
		};

		aips@53f00000 { /* AIPS2 */
		bus@53f00000 { /* AIPS2 */
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
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