Commit 96800f03 authored by Andy Yan's avatar Andy Yan Committed by Heiko Stuebner
Browse files

ARM: dts: rockchip: rename core dtsi from RK1108 to RV1108 



Rockchip finally named the SOC as RV1108, so change it
for compatible.

Signed-off-by: default avatarAndy Yan <andy.yan@rock-chips.com>

[adapt include in rk1108-evb.dts to not introduce errors]
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 95b840af

arch/arm/boot/dts/rk1108-evb.dts

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ 


/dts-v1/;



#include "rk1108.dtsi"

#include "rv1108.dtsi"



/ {

	model = "Rockchip RK1108 Evaluation board";

arch/arm/boot/dts/rk1108.dtsi→arch/arm/boot/dts/rv1108.dtsi

+10 −10
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ 
	#address-cells = <1>;

	#size-cells = <1>;



	compatible = "rockchip,rk1108";

	compatible = "rockchip,rv1108";



	interrupt-parent = <&gic>;
@@ -113,7 +113,7 @@ 
	};



	uart2: serial@10210000 {

		compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";

		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";

		reg = <0x10210000 0x100>;

		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;
@@ -127,7 +127,7 @@ 
	};



	uart1: serial@10220000 {

		compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";

		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";

		reg = <0x10220000 0x100>;

		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;
@@ -141,7 +141,7 @@ 
	};



	uart0: serial@10230000 {

		compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";

		compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";

		reg = <0x10230000 0x100>;

		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;
@@ -155,17 +155,17 @@ 
	};



	grf: syscon@10300000 {

		compatible = "rockchip,rk1108-grf", "syscon";

		compatible = "rockchip,rv1108-grf", "syscon";

		reg = <0x10300000 0x1000>;

	};



	pmugrf: syscon@20060000 {

		compatible = "rockchip,rk1108-pmugrf", "syscon";

		compatible = "rockchip,rv1108-pmugrf", "syscon";

		reg = <0x20060000 0x1000>;

	};



	cru: clock-controller@20200000 {

		compatible = "rockchip,rk1108-cru";

		compatible = "rockchip,rv1108-cru";

		reg = <0x20200000 0x1000>;

		rockchip,grf = <&grf>;

		#clock-cells = <1>;
@@ -173,7 +173,7 @@ 
	};



	emmc: dwmmc@30110000 {

		compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";

		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,

			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
@@ -185,7 +185,7 @@ 
	};



	sdio: dwmmc@30120000 {

		compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";

		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,

			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
@@ -197,7 +197,7 @@ 
	};



	sdmmc: dwmmc@30130000 {

		compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";

		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 100000000>;

		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,

			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;

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