Commit 964e3717 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.19-tag1' of... 

Merge tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates for v4.19 from Geert Uytterhoeven:

  - Add support for Crypto Engine clocks on R-Car H3
  - Add support for the new RZ/N1D SoC

* tag 'clk-renesas-for-v4.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Renesas R9A06G032 clock driver
  dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation
  dt-bindings: clock: Add the r9a06g032-sysctrl.h file
  clk: renesas: r8a7795: Add CCREE clock
  clk: renesas: r8a7795: Add CR clock
parents ce397d21 4c3d8852

Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt

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* Renesas R9A06G032 SYSCTRL



Required Properties:



  - compatible: Must be:

    - "renesas,r9a06g032-sysctrl"

  - reg: Base address and length of the SYSCTRL IO block.

  - #clock-cells: Must be 1

  - clocks: References to the parent clocks:

	- external 40mhz crystal.

	- external (optional) 32.768khz

	- external (optional) jtag input

	- external (optional) RGMII_REFCLK

  - clock-names: Must be:

        clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";



Examples

--------



  - SYSCTRL node:



	sysctrl: system-controller@4000c000 {

		compatible = "renesas,r9a06g032-sysctrl";

		reg = <0x4000c000 0x1000>;

		#clock-cells = <1>;



		clocks = <&ext_mclk>, <&ext_rtc_clk>,

				<&ext_jtag_clk>, <&ext_rgmii_ref>;

		clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";

	};



  - Other nodes can use the clocks provided by SYSCTRL as in:



	#include <dt-bindings/clock/r9a06g032-sysctrl.h>

	uart0: serial@40060000 {

		compatible = "snps,dw-apb-uart";

		reg = <0x40060000 0x400>;

		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

		clocks = <&sysctrl R9A06G032_CLK_UART0>;

		clock-names = "baudclk";

	};

drivers/clk/renesas/Kconfig

+6 −0
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@@ -21,6 +21,7 @@ config CLK_RENESAS 
	select CLK_R8A77980 if ARCH_R8A77980

	select CLK_R8A77990 if ARCH_R8A77990

	select CLK_R8A77995 if ARCH_R8A77995

	select CLK_R9A06G032 if ARCH_R9A06G032

	select CLK_SH73A0 if ARCH_SH73A0



if CLK_RENESAS
@@ -125,6 +126,11 @@ config CLK_R8A77995 
	bool "R-Car D3 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R9A06G032

	bool "Renesas R9A06G032 clock driver"

	help

	  This is a driver for R9A06G032 clocks



config CLK_SH73A0

	bool "SH-Mobile AG5 clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP

drivers/clk/renesas/Makefile

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@@ -20,6 +20,7 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o

obj-$(CONFIG_CLK_R9A06G032)		+= r9a06g032-clocks.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o



# Family

drivers/clk/renesas/r8a7795-cpg-mssr.c

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@@ -103,6 +103,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 
	DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),



	DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),

	DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),

	DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),



	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
@@ -132,6 +133,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S0D3),

	DEF_MOD("sceg-pub",		 229,	R8A7795_CLK_CR),

	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7795_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7795_CLK_R),

drivers/clk/renesas/r9a06g032-clocks.c

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