Commit 963cee55 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: change memory training to common function 



Change memory training init and finit a common function, as it only have
software behavior do not relay on the IP version of PSP.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 19822264

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

+40 −2
Original line number Diff line number Diff line
@@ -115,6 +115,44 @@ static int psp_early_init(void *handle) 
	return 0;

}



static void psp_memory_training_fini(struct psp_context *psp)

{

	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;



	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;

	kfree(ctx->sys_cache);

	ctx->sys_cache = NULL;

}



static int psp_memory_training_init(struct psp_context *psp)

{

	int ret;

	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;



	if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {

		DRM_DEBUG("memory training is not supported!\n");

		return 0;

	}



	ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);

	if (ctx->sys_cache == NULL) {

		DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");

		ret = -ENOMEM;

		goto Err_out;

	}



	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",

		  ctx->train_data_size,

		  ctx->p2c_train_data_offset,

		  ctx->c2p_train_data_offset);

	ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;

	return 0;



Err_out:

	psp_memory_training_fini(psp);

	return ret;

}



static int psp_sw_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -127,7 +165,7 @@ static int psp_sw_init(void *handle) 
		return ret;

	}



	ret = psp_mem_training_init(psp);

	ret = psp_memory_training_init(psp);

	if (ret) {

		DRM_ERROR("Failed to initialize memory training!\n");

		return ret;
@@ -152,7 +190,7 @@ static int psp_sw_fini(void *handle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	psp_mem_training_fini(&adev->psp);

	psp_memory_training_fini(&adev->psp);

	release_firmware(adev->psp.sos_fw);

	adev->psp.sos_fw = NULL;

	release_firmware(adev->psp.asd_fw);

drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h

+0 −6
Original line number Diff line number Diff line
@@ -95,8 +95,6 @@ struct psp_funcs 
			    enum psp_ring_type ring_type);

	bool (*smu_reload_quirk)(struct psp_context *psp);

	int (*mode1_reset)(struct psp_context *psp);

	int (*mem_training_init)(struct psp_context *psp);

	void (*mem_training_fini)(struct psp_context *psp);

	int (*mem_training)(struct psp_context *psp, uint32_t ops);

	uint32_t (*ring_get_wptr)(struct psp_context *psp);

	void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
@@ -306,10 +304,6 @@ struct amdgpu_psp_funcs { 
		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)

#define psp_mode1_reset(psp) \

		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)

#define psp_mem_training_init(psp) \

	((psp)->funcs->mem_training_init ? (psp)->funcs->mem_training_init((psp)) : 0)

#define psp_mem_training_fini(psp) \

	((psp)->funcs->mem_training_fini ? (psp)->funcs->mem_training_fini((psp)) : 0)

#define psp_mem_training(psp, ops) \

	((psp)->funcs->mem_training ? (psp)->funcs->mem_training((psp), (ops)) : 0)

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c

+0 −40
Original line number Diff line number Diff line
@@ -555,44 +555,6 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg) 
	return ret;

}



static void psp_v11_0_memory_training_fini(struct psp_context *psp)

{

	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;



	ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;

	kfree(ctx->sys_cache);

	ctx->sys_cache = NULL;

}



static int psp_v11_0_memory_training_init(struct psp_context *psp)

{

	int ret;

	struct psp_memory_training_context *ctx = &psp->mem_train_ctx;



	if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {

		DRM_DEBUG("memory training is not supported!\n");

		return 0;

	}



	ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);

	if (ctx->sys_cache == NULL) {

		DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");

		ret = -ENOMEM;

		goto Err_out;

	}



	DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",

		  ctx->train_data_size,

		  ctx->p2c_train_data_offset,

		  ctx->c2p_train_data_offset);

	ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;

	return 0;



Err_out:

	psp_v11_0_memory_training_fini(psp);

	return ret;

}



/*

 * save and restore proces

 */
@@ -820,8 +782,6 @@ static const struct psp_funcs psp_v11_0_funcs = { 
	.ring_stop = psp_v11_0_ring_stop,

	.ring_destroy = psp_v11_0_ring_destroy,

	.mode1_reset = psp_v11_0_mode1_reset,

	.mem_training_init = psp_v11_0_memory_training_init,

	.mem_training_fini = psp_v11_0_memory_training_fini,

	.mem_training = psp_v11_0_memory_training,

	.ring_get_wptr = psp_v11_0_ring_get_wptr,

	.ring_set_wptr = psp_v11_0_ring_set_wptr,

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