Commit 960e9836 authored Jul 30, 2019 by Vandita Kulkarni Committed by Uma Shankar Aug 08, 2019

drm/i915/tgl/dsi: Set latency PCS_DW1 for tgl



Latency programming remains same as that of ICL and
setting latency otimization for PCS_DW1 lanes is same as
that of EHL, hence extending it to TGL.

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190730073648.5157-3-vandita.kulkarni@intel.com

parent 3522a33a

drivers/gpu/drm/i915/display/icl_dsi.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -403,8 +403,8 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
		tmp \|= FRC_LATENCY_OPTIM_VAL(0x5);
		I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp);

		/* For EHL set latency optimization for PCS_DW1 lanes */
		if (IS_ELKHARTLAKE(dev_priv)) {
		/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
		if (IS_ELKHARTLAKE(dev_priv) \|\| (INTEL_GEN(dev_priv) >= 12)) {
		tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy));
		tmp &= ~LATENCY_OPTIM_MASK;
		tmp \|= LATENCY_OPTIM_VAL(0);

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