Merge branch 'fixes' into next (960e3708) · Commits · 戴 / test

Documentation/features/debug/debug-vm-pgtable/arch-support.txt

+1 −1

+3 −1

Original line number	Diff line number	Diff line
		@@ -49,16 +49,18 @@ Register preservation rules
		Register preservation rules match the ELF ABI calling sequence with the
		following differences:

		=========== ============= ========================================
		--- For the sc instruction, differences with the ELF ABI ---
		=========== ============= ========================================
		r0 Volatile (System call number.)
		r3 Volatile (Parameter 1, and return value.)
		r4-r8 Volatile (Parameters 2-6.)
		cr0 Volatile (cr0.SO is the return error condition.)
		cr1, cr5-7 Nonvolatile
		lr Nonvolatile
		=========== ============= ========================================

		--- For the scv 0 instruction, differences with the ELF ABI ---
		=========== ============= ========================================
		r0 Volatile (System call number.)
		r3 Volatile (Parameter 1, and return value.)
		r4-r8 Volatile (Parameters 2-6.)

+12 −1

Original line number	Diff line number	Diff line
		@@ -116,7 +116,6 @@ config PPC
		#
		select ARCH_32BIT_OFF_T if PPC32
		select ARCH_HAS_DEBUG_VIRTUAL
		select ARCH_HAS_DEBUG_VM_PGTABLE
		select ARCH_HAS_DEVMEM_IS_ALLOWED
		select ARCH_HAS_ELF_RANDOMIZE
		select ARCH_HAS_FORTIFY_SOURCE
		@@ -860,6 +859,18 @@ config PPC_SUBPAGE_PROT

		If unsure, say N here.

		config PPC_PROT_SAO_LPAR
		bool "Support PROT_SAO mappings in LPARs"
		depends on PPC_BOOK3S_64
		help
		This option adds support for PROT_SAO mappings from userspace
		inside LPARs on supported CPUs.

		This may cause issues when performing guest migration from
		a CPU that supports SAO to one that does not.

		If unsure, say N here.

		config PPC_COPRO_BASE
		bool

+5 −5

Original line number	Diff line number	Diff line
		@@ -239,14 +239,14 @@ static inline void early_init_mmu_secondary(void)

		extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
		phys_addr_t first_memblock_size);
		extern void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
		phys_addr_t first_memblock_size);
		static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
		phys_addr_t first_memblock_size)
		{
		if (early_radix_enabled())
		return radix__setup_initial_memory_limit(first_memblock_base,
		first_memblock_size);
		/*
		* Hash has more strict restrictions. At this point we don't
		* know which translations we will pick. Hence go with hash
		* restrictions.
		*/
		return hash__setup_initial_memory_limit(first_memblock_base,
		first_memblock_size);
		}

+3 −5

Original line number	Diff line number	Diff line
		@@ -20,13 +20,9 @@
		#define _PAGE_RW (_PAGE_READ \| _PAGE_WRITE)
		#define _PAGE_RWX (_PAGE_READ \| _PAGE_WRITE \| _PAGE_EXEC)
		#define _PAGE_PRIVILEGED 0x00008 /* kernel access only */

		#define _PAGE_CACHE_CTL 0x00030 /* Bits for the folowing cache modes */
		/* No bits set is normal cacheable memory */
		/* 0x00010 unused, is SAO bit on radix POWER9 */
		#define _PAGE_SAO 0x00010 /* Strong access order */
		#define _PAGE_NON_IDEMPOTENT 0x00020 /* non idempotent memory */
		#define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */

		#define _PAGE_DIRTY 0x00080 /* C: page changed */
		#define _PAGE_ACCESSED 0x00100 /* R: page referenced */
		/*
		@@ -828,6 +824,8 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
		return hash__set_pte_at(mm, addr, ptep, pte, percpu);
		}

		#define _PAGE_CACHE_CTL (_PAGE_SAO \| _PAGE_NON_IDEMPOTENT \| _PAGE_TOLERANT)

		#define pgprot_noncached pgprot_noncached
		static inline pgprot_t pgprot_noncached(pgprot_t prot)
		{