Merge tag 'omap-fixes-against-v3.17-rc3' of...

* Toshiba TC3589x multi-purpose expander

The Toshiba TC3589x series are I2C-based MFD devices which may expose the

following built-in devices: gpio, keypad, rotator (vibrator), PWM (for

e.g. LEDs or vibrators) The included models are:

- TC35890

- TC35892

- TC35893

- TC35894

- TC35895

- TC35896

Required properties:

 - compatible : must be "toshiba,tc35890", "toshiba,tc35892", "toshiba,tc35893",

   "toshiba,tc35894", "toshiba,tc35895" or "toshiba,tc35896"

 - reg : I2C address of the device

 - interrupt-parent : specifies which IRQ controller we're connected to

 - interrupts : the interrupt on the parent the controller is connected to

 - interrupt-controller : marks the device node as an interrupt controller

 - #interrupt-cells : should be <1>, the first cell is the IRQ offset on this

   TC3589x interrupt controller.

Optional nodes:

- GPIO

  This GPIO module inside the TC3589x has 24 (TC35890, TC35892) or 20

  (other models) GPIO lines.

 - compatible : must be "toshiba,tc3589x-gpio"

 - interrupts : interrupt on the parent, which must be the tc3589x MFD device

 - interrupt-controller : marks the device node as an interrupt controller

 - #interrupt-cells : should be <2>, the first cell is the IRQ offset on this

   TC3589x GPIO interrupt controller, the second cell is the interrupt flags

   in accordance with <dt-bindings/interrupt-controller/irq.h>. The following

   flags are valid:

   - IRQ_TYPE_LEVEL_LOW

   - IRQ_TYPE_LEVEL_HIGH

   - IRQ_TYPE_EDGE_RISING

   - IRQ_TYPE_EDGE_FALLING

   - IRQ_TYPE_EDGE_BOTH

 - gpio-controller : marks the device node as a GPIO controller

 - #gpio-cells : should be <2>, the first cell is the GPIO offset on this

   GPIO controller, the second cell is the flags.

- Keypad

  This keypad is the same on all variants, supporting up to 96 different

  keys. The linux-specific properties are modeled on those already existing

  in other input drivers.

 - compatible : must be "toshiba,tc3589x-keypad"

 - debounce-delay-ms : debounce interval in milliseconds

 - keypad,num-rows : number of rows in the matrix, see

   bindings/input/matrix-keymap.txt

 - keypad,num-columns : number of columns in the matrix, see

   bindings/input/matrix-keymap.txt

 - linux,keymap: the definition can be found in

   bindings/input/matrix-keymap.txt

 - linux,no-autorepeat: do no enable autorepeat feature.

 - linux,wakeup: use any event on keypad as wakeup event.

Example:

tc35893@44 {

	compatible = "toshiba,tc35893";

	reg = <0x44>;

	interrupt-parent = <&gpio6>;

	interrupts = <26 IRQ_TYPE_EDGE_RISING>;

	interrupt-controller;

	#interrupt-cells = <1>;

	tc3589x_gpio {

		compatible = "toshiba,tc3589x-gpio";

		interrupts = <0>;

		interrupt-controller;

		#interrupt-cells = <2>;

		gpio-controller;

		#gpio-cells = <2>;

	};

	tc3589x_keypad {

		compatible = "toshiba,tc3589x-keypad";

		interrupts = <6>;

		debounce-delay-ms = <4>;

		keypad,num-columns = <8>;

		keypad,num-rows = <8>;

		linux,no-autorepeat;

		linux,wakeup;

		linux,keymap = <0x0301006b

				0x04010066

				0x06040072

				0x040200d7

				0x0303006a

				0x0205000e

				0x0607008b

				0x0500001c

				0x0403000b

				0x03040034

				0x05020067

				0x0305006c

				0x040500e7

				0x0005009e

				0x06020073

				0x01030039

				0x07060069

				0x050500d9>;

	};

};

		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;

		interrupts = <0 32 0x4>;

		interrupts = <0 16 0x4>;

		pinctrl-names = "default";

		pinctrl-0 = <&gsbi5_uart_default>;

				     size_t size, int flags,

				     const char *exp_name)

   If this succeeds, dma_buf_export allocates a dma_buf structure, and returns a

   pointer to the same. It also associates an anonymous file with this buffer,

   so it can be exported. On failure to allocate the dma_buf object, it returns

   NULL.

   If this succeeds, dma_buf_export_named allocates a dma_buf structure, and

   returns a pointer to the same. It also associates an anonymous file with this

   buffer, so it can be exported. On failure to allocate the dma_buf object,

   it returns NULL.

   'exp_name' is the name of exporter - to facilitate information while

   debugging.

   drivers and/or processes.

   Interface:

      int dma_buf_fd(struct dma_buf *dmabuf)

      int dma_buf_fd(struct dma_buf *dmabuf, int flags)

   This API installs an fd for the anonymous file associated with this buffer;

   returns either 'fd', or error.

   "dma_buf->ops->" indirection from the users of this interface.

   In struct dma_buf_ops, unmap_dma_buf is defined as

      void (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *);

      void (*unmap_dma_buf)(struct dma_buf_attachment *,

                            struct sg_table *,

                            enum dma_data_direction);

   unmap_dma_buf signifies the end-of-DMA for the attachment provided. Like

   map_dma_buf, this API also must be implemented by the exporter.

a remote system.

Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64,

and s390x architectures.

s390x and arm architectures.

When the system kernel boots, it reserves a small section of memory for

the dump-capture kernel. This ensures that ongoing Direct Memory Access

2) Or use the system kernel binary itself as dump-capture kernel and there is

   no need to build a separate dump-capture kernel. This is possible

   only with the architectures which support a relocatable kernel. As

   of today, i386, x86_64, ppc64 and ia64 architectures support relocatable

   of today, i386, x86_64, ppc64, ia64 and arm architectures support relocatable

   kernel.

Building a relocatable kernel is advantageous from the point of view that

  kernel will be aligned to 64Mb, so if the start address is not then

  any space below the alignment point will be wasted.

Dump-capture kernel config options (Arch Dependent, arm)

----------------------------------------------------------

-   To use a relocatable kernel,

    Enable "AUTO_ZRELADDR" support under "Boot" options:

    AUTO_ZRELADDR=y

Extended crashkernel syntax

===========================

    crashkernel=<range1>:<size1>[,<range2>:<size2>,...][@offset]

    range=start-[end]

Please note, on arm, the offset is required.

    crashkernel=<range1>:<size1>[,<range2>:<size2>,...]@offset

    range=start-[end]

    'start' is inclusive and 'end' is exclusive.

For example:

   on the memory consumption of the kdump system. In general this is not

   dependent on the memory size of the production system.

   On arm, use "crashkernel=Y@X". Note that the start address of the kernel

   will be aligned to 128MiB (0x08000000), so if the start address is not then

   any space below the alignment point may be overwritten by the dump-capture kernel,

   which means it is possible that the vmcore is not that precise as expected.

Load the Dump-capture Kernel

============================

	- Use vmlinux or vmlinuz.gz

For s390x:

	- Use image or bzImage

For arm:

	- Use zImage

If you are using a uncompressed vmlinux image then use following command

to load dump-capture kernel.

   --initrd=<initrd-for-dump-capture-kernel> \

   --append="root=<root-dev> <arch-specific-options>"

If you are using a compressed zImage, then use following command

to load dump-capture kernel.

   kexec --type zImage -p <dump-capture-kernel-bzImage> \

   --initrd=<initrd-for-dump-capture-kernel> \

   --dtb=<dtb-for-dump-capture-kernel> \

   --append="root=<root-dev> <arch-specific-options>"

Please note, that --args-linux does not need to be specified for ia64.

It is planned to make this a no-op on that architecture, but for now

it should be omitted

For s390x:

	"1 maxcpus=1 cgroup_disable=memory"

For arm:

	"1 maxcpus=1 reset_devices"

Notes on loading the dump-capture kernel:

* By default, the ELF headers are stored in ELF64 format to support

-------------------

this_cpu operations are a way of optimizing access to per cpu

variables associated with the *currently* executing processor through

the use of segment registers (or a dedicated register where the cpu

permanently stored the beginning of the per cpu area for a specific

processor).

variables associated with the *currently* executing processor. This is

done through the use of segment registers (or a dedicated register where

the cpu permanently stored the beginning of the per cpu	area for a

specific processor).

The this_cpu operations add a per cpu variable offset to the processor

this_cpu operations add a per cpu variable offset to the processor

specific per cpu base and encode that operation in the instruction

operating on the per cpu variable.

This means there are no atomicity issues between the calculation of

This means that there are no atomicity issues between the calculation of

the offset and the operation on the data. Therefore it is not

necessary to disable preempt or interrupts to ensure that the

necessary to disable preemption or interrupts to ensure that the

processor is not changed between the calculation of the address and

the operation on the data.

Read-modify-write operations are of particular interest. Frequently

processors have special lower latency instructions that can operate

without the typical synchronization overhead but still provide some

sort of relaxed atomicity guarantee. The x86 for example can execute

RMV (Read Modify Write) instructions like inc/dec/cmpxchg without the

without the typical synchronization overhead, but still provide some

sort of relaxed atomicity guarantees. The x86, for example, can execute

RMW (Read Modify Write) instructions like inc/dec/cmpxchg without the

lock prefix and the associated latency penalty.

Access to the variable without the lock prefix is not synchronized but

processor should be accessing that variable and therefore there are no

concurrency issues with other processors in the system.

Please note that accesses by remote processors to a per cpu area are

exceptional situations and may impact performance and/or correctness

(remote write operations) of local RMW operations via this_cpu_*.

The main use of the this_cpu operations has been to optimize counter

operations.

The following this_cpu() operations with implied preemption protection

are defined. These operations can be used without worrying about

preemption and interrupts.

	this_cpu_add()

	this_cpu_read(pcp)

	this_cpu_write(pcp, val)

	this_cpu_add(pcp, val)

	this_cpu_and(pcp, val)

	this_cpu_or(pcp, val)

	this_cpu_add_return(pcp, val)

	this_cpu_xchg(pcp, nval)

	this_cpu_cmpxchg(pcp, oval, nval)

	this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

	this_cpu_sub(pcp, val)

	this_cpu_inc(pcp)

	this_cpu_dec(pcp)

	this_cpu_sub_return(pcp, val)

	this_cpu_inc_return(pcp)

	this_cpu_dec_return(pcp)

Inner working of this_cpu operations

------------------------------------

On x86 the fs: or the gs: segment registers contain the base of the

per cpu area. It is then possible to simply use the segment override

to relocate a per cpu relative address to the proper per cpu area for

prevent the kernel from moving the thread to a different processor

while the calculation is performed.

The main use of the this_cpu operations has been to optimize counter

operations.

Consider the following this_cpu operation:

	this_cpu_inc(x)

results in the following single instruction (no lock prefix!)

The above results in the following single instruction (no lock prefix!)

	inc gs:[x]

instead of the following operations required if there is no segment

register.

register:

	int *y;

	int cpu;

the same code paths.  Since each processor has its own per cpu

variables no concurrent cache line updates take place. The price that

has to be paid for this optimization is the need to add up the per cpu

counters when the value of the counter is needed.

counters when the value of a counter is needed.

Special operations:

of the per cpu variable that belongs to the currently executing

processor.  this_cpu_ptr avoids multiple steps that the common

get_cpu/put_cpu sequence requires. No processor number is

available. Instead the offset of the local per cpu area is simply

available. Instead, the offset of the local per cpu area is simply

added to the per cpu offset.

Note that this operation is usually used in a code segment when

preemption has been disabled. The pointer is then used to

access local per cpu data in a critical section. When preemption

is re-enabled this pointer is usually no longer useful since it may

no longer point to per cpu data of the current processor.

Per cpu variables and offsets

operations is invalid and will generally be treated like a NULL

pointer dereference.

In the context of per cpu operations

	DEFINE_PER_CPU(int, x);

	x is a per cpu variable. Most this_cpu operations take a cpu

	variable.

In the context of per cpu operations the above implies that x is a per

cpu variable. Most this_cpu operations take a cpu variable.

	&x is the *offset* a per cpu variable. this_cpu_ptr() takes

	the offset of a per cpu variable which makes this look a bit

	strange.

	int __percpu *p = &x;

&x and hence p is the *offset* of a per cpu variable. this_cpu_ptr()

takes the offset of a per cpu variable which makes this look a bit

strange.

Operations on a field of a per cpu structure

	struct s __percpu *ps = &p;

	z = this_cpu_dec(ps->m);

	this_cpu_dec(ps->m);

	z = this_cpu_inc_return(ps->n);

Variants of this_cpu ops

-------------------------

this_cpu ops are interrupt safe. Some architecture do not support

this_cpu ops are interrupt safe. Some architectures do not support

these per cpu local operations. In that case the operation must be

replaced by code that disables interrupts, then does the operations

that are guaranteed to be atomic and then reenable interrupts. Doing

that are guaranteed to be atomic and then re-enable interrupts. Doing

so is expensive. If there are other reasons why the scheduler cannot

change the processor we are executing on then there is no reason to

disable interrupts. For that purpose the __this_cpu operations are

provided. For example.

	__this_cpu_inc(x);

Will increment x and will not fallback to code that disables

disable interrupts. For that purpose the following __this_cpu operations

are provided.

These operations have no guarantee against concurrent interrupts or

preemption. If a per cpu variable is not used in an interrupt context

and the scheduler cannot preempt, then they are safe. If any interrupts

still occur while an operation is in progress and if the interrupt too

modifies the variable, then RMW actions can not be guaranteed to be

safe.

	__this_cpu_add()

	__this_cpu_read(pcp)

	__this_cpu_write(pcp, val)

	__this_cpu_add(pcp, val)

	__this_cpu_and(pcp, val)

	__this_cpu_or(pcp, val)

	__this_cpu_add_return(pcp, val)

	__this_cpu_xchg(pcp, nval)

	__this_cpu_cmpxchg(pcp, oval, nval)

	__this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2)

	__this_cpu_sub(pcp, val)

	__this_cpu_inc(pcp)

	__this_cpu_dec(pcp)

	__this_cpu_sub_return(pcp, val)

	__this_cpu_inc_return(pcp)

	__this_cpu_dec_return(pcp)

Will increment x and will not fall-back to code that disables

interrupts on platforms that cannot accomplish atomicity through

address relocation and a Read-Modify-Write operation in the same

instruction.

&this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n)

--------------------------------------------

The first operation takes the offset and forms an address and then

adds the offset of the n field.

adds the offset of the n field. This may result in two add

instructions emitted by the compiler.

The second one first adds the two offsets and then does the

relocation.  IMHO the second form looks cleaner and has an easier time

this_cpu_read() and friends are used.

Christoph Lameter, April 3rd, 2013

Remote access to per cpu data

------------------------------

Per cpu data structures are designed to be used by one cpu exclusively.

If you use the variables as intended, this_cpu_ops() are guaranteed to

be "atomic" as no other CPU has access to these data structures.

There are special cases where you might need to access per cpu data

structures remotely. It is usually safe to do a remote read access

and that is frequently done to summarize counters. Remote write access

something which could be problematic because this_cpu ops do not

have lock semantics. A remote write may interfere with a this_cpu

RMW operation.

Remote write accesses to percpu data structures are highly discouraged

unless absolutely necessary. Please consider using an IPI to wake up

the remote CPU and perform the update to its per cpu area.

To access per-cpu data structure remotely, typically the per_cpu_ptr()

function is used:

	DEFINE_PER_CPU(struct data, datap);

	struct data *p = per_cpu_ptr(&datap, cpu);

This makes it explicit that we are getting ready to access a percpu

area remotely.

You can also do the following to convert the datap offset to an address

	struct data *p = this_cpu_ptr(&datap);

but, passing of pointers calculated via this_cpu_ptr to other cpus is

unusual and should be avoided.

Remote access are typically only for reading the status of another cpus

per cpu data. Write accesses can cause unique problems due to the

relaxed synchronization requirements for this_cpu operations.

One example that illustrates some concerns with write operations is

the following scenario that occurs because two per cpu variables

share a cache-line but the relaxed synchronization is applied to

only one process updating the cache-line.

Consider the following example

	struct test {

		atomic_t a;

		int b;

	};

	DEFINE_PER_CPU(struct test, onecacheline);

There is some concern about what would happen if the field 'a' is updated

remotely from one processor and the local processor would use this_cpu ops

to update field b. Care should be taken that such simultaneous accesses to

data within the same cache line are avoided. Also costly synchronization

may be necessary. IPIs are generally recommended in such scenarios instead

of a remote write to the per cpu area of another processor.

Even in cases where the remote writes are rare, please bear in

mind that a remote write will evict the cache line from the processor

that most likely will access it. If the processor wakes up and finds a

missing local cache line of a per cpu area, its performance and hence

the wake up times will be affected.

Christoph Lameter, August 4th, 2014

Pranith Kumar, Aug 2nd, 2014