Commit 95eb940c authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'samsung-dt-odroid-xu-4.8' of... 

Merge tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Topic branch for adding Exynos 5410 Odroid XU board for v4.8.

This brings support for Hardkernel's Odroid XU board.  It was the first
design with big.LITTLE SoC from Samsung: Exynos5410.  The board is not
very popular.  Newer XU3 and XU4 got more attention.

Board details:
1. Exynos5410 octa-core (A15+A7, however as of now only one cluster is
   enabled),
2. 2 GB DDR3 RAM,
3. PowerVR SGX544MP3 GPU (not enabled in DTS),
4. USB 3.0 Host x 1, USB 3.0 OTG x 1, USB 2.0 Host x 4,
5. HDMI 1.4a, MIPI DSI and Display Port (Display Port not on all of
   revisions though),
6. eMMC 4.5 and microSD slots.

* tag 'samsung-dt-odroid-xu-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux

: (28 commits)
  ARM: dts: exynos: Add watchdog and Security SubSystem to Exynos5410
  ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board
  ARM: dts: exynos: Add Thermal Management Unit to Exynos5410
  ARM: dts: exynos: Interrupt for USB DWC3-1 differs between Exynos5420 and 5410
  dt-bindings: clock: Add watchdog and SSS clock IDs to Exynos5410
  dt-bindings: clock: Add TMU clock ID to Exynos5410
  ARM: dts: exynos: Add RTC and I2C to Exynos5410
  ARM: dts: exynos: Add I2C, PWM and UART pinctrl to Exynos5410
  ARM: dts: exynos: Move HSI2C nodes to exynos54xx.dtsi
  ARM: dts: exynos: Add initial support for Odroid XU board
  ARM: dts: exynos: Add USB to Exynos5410
  ARM: dts: exynos: Move common Exynos5410/542x/5800 nodes to new DTSI
  ARM: dts: exynos: MCT is not an interrupt controller and extend length of iomap
  ARM: dts: exynos: Enable UART3 on Exynos5410
  ARM: dts: exynos: Include common exynos5 in exynos5410.dtsi
  ARM: dts: exynos: Move Exynos5250 and Exynos5420 nodes under soc
  ARM: dts: exynos: Use phandle to get parent node in exynos5250-snow
  ARM: dts: exynos: Prepare for inclusion of exynos5.dtsi in exynos5410.dtsi
  ARM: dts: exynos: Move common nodes to exynos5.dtsi
  ARM: dts: exynos: Split Odroid XU3 LEDs to separate DTSI
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents effd7862 b8bd7e23

Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ Required root node properties: 
	- "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.

	- "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.

	- "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.

	- "hardkernel,odroid-xu"  - for Exynos5410-based Hardkernel Odroid XU.

	- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.

	- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel

					 Odroid XU3 Lite board.

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -134,6 +134,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ 
	exynos5250-snow-rev5.dtb \

	exynos5250-spring.dtb \

	exynos5260-xyref5260.dtb \

	exynos5410-odroidxu.dtb \

	exynos5410-smdk5410.dtb \

	exynos5420-arndale-octa.dtb \

	exynos5420-peach-pit.dtb \

arch/arm/boot/dts/exynos5.dtsi

+139 −76
Original line number Diff line number Diff line
@@ -20,18 +20,28 @@ 
	interrupt-parent = <&gic>;



	aliases {

		i2c0 = &i2c_0;

		i2c1 = &i2c_1;

		i2c2 = &i2c_2;

		i2c3 = &i2c_3;

		serial0 = &serial_0;

		serial1 = &serial_1;

		serial2 = &serial_2;

		serial3 = &serial_3;

	};



	soc: soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		chipid@10000000 {

			compatible = "samsung,exynos4210-chipid";

			reg = <0x10000000 0x100>;

		};



	memory-controller@12250000 {

		sromc: memory-controller@12250000 {

			compatible = "samsung,exynos4210-srom";

			reg = <0x12250000 0x14>;

		};
@@ -63,6 +73,11 @@ 
			interrupts = <1 9 0xf04>;

		};



		sysreg_system_controller: syscon@10050000 {

			compatible = "samsung,exynos5-sysreg", "syscon";

			reg = <0x10050000 0x5000>;

		};



		serial_0: serial@12C00000 {

			compatible = "samsung,exynos4210-uart";

			reg = <0x12C00000 0x100>;
@@ -87,6 +102,53 @@ 
			interrupts = <0 54 0>;

		};



		i2c_0: i2c@12C60000 {

			compatible = "samsung,s3c2440-i2c";

			reg = <0x12C60000 0x100>;

			interrupts = <0 56 0>;

			#address-cells = <1>;

			#size-cells = <0>;

			samsung,sysreg-phandle = <&sysreg_system_controller>;

			status = "disabled";

		};



		i2c_1: i2c@12C70000 {

			compatible = "samsung,s3c2440-i2c";

			reg = <0x12C70000 0x100>;

			interrupts = <0 57 0>;

			#address-cells = <1>;

			#size-cells = <0>;

			samsung,sysreg-phandle = <&sysreg_system_controller>;

			status = "disabled";

		};



		i2c_2: i2c@12C80000 {

			compatible = "samsung,s3c2440-i2c";

			reg = <0x12C80000 0x100>;

			interrupts = <0 58 0>;

			#address-cells = <1>;

			#size-cells = <0>;

			samsung,sysreg-phandle = <&sysreg_system_controller>;

			status = "disabled";

		};



		i2c_3: i2c@12C90000 {

			compatible = "samsung,s3c2440-i2c";

			reg = <0x12C90000 0x100>;

			interrupts = <0 59 0>;

			#address-cells = <1>;

			#size-cells = <0>;

			samsung,sysreg-phandle = <&sysreg_system_controller>;

			status = "disabled";

		};



		pwm: pwm@12DD0000 {

			compatible = "samsung,exynos4210-pwm";

			reg = <0x12DD0000 0x100>;

			samsung,pwm-outputs = <0>, <1>, <2>, <3>;

			#pwm-cells = <3>;

		};



		rtc: rtc@101E0000 {

			compatible = "samsung,s3c6410-rtc";

			reg = <0x101E0000 0x100>;
@@ -114,3 +176,4 @@ 
			status = "disabled";

		};

	};

};

arch/arm/boot/dts/exynos5250-snow-common.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -61,7 +61,7 @@ 
		#address-cells = <1>;

		#size-cells = <0>;



		i2c-parent = <&{/i2c@12CA0000}>;

		i2c-parent = <&i2c_4>;



		our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;

		their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;

arch/arm/boot/dts/exynos5250.dtsi

+832 −869
Original line number Diff line number Diff line
@@ -37,10 +37,6 @@ 
		mshc1 = &mmc_1;

		mshc2 = &mmc_2;

		mshc3 = &mmc_3;

		i2c0 = &i2c_0;

		i2c1 = &i2c_1;

		i2c2 = &i2c_2;

		i2c3 = &i2c_3;

		i2c4 = &i2c_4;

		i2c5 = &i2c_5;

		i2c6 = &i2c_6;
@@ -96,6 +92,7 @@ 
		};

	};



	soc: soc {

		sysram@02020000 {

			compatible = "mmio-sram";

			reg = <0x02020000 0x30000>;
@@ -157,9 +154,10 @@ 
				     <1 14 0xf08>,

				     <1 11 0xf08>,

				     <1 10 0xf08>;

		/* Unfortunately we need this since some versions of U-Boot

		 * on Exynos don't set the CNTFRQ register, so we need the

		 * value from DT.

			/*

			 * Unfortunately we need this since some versions

			 * of U-Boot on Exynos don't set the CNTFRQ register,

			 * so we need the value from DT.

			 */

			clock-frequency = <24000000>;

		};
@@ -235,11 +233,6 @@ 
			interrupt-parent = <&gic>;

		};



	sysreg_system_controller: syscon@10050000 {

		compatible = "samsung,exynos5-sysreg", "syscon";

		reg = <0x10050000 0x5000>;

	};



		watchdog@101D0000 {

			compatible = "samsung,exynos5250-wdt";

			reg = <0x101D0000 0x100>;
@@ -287,25 +280,6 @@ 
			#include "exynos4412-tmu-sensor-conf.dtsi"

		};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive = <0>;

			polling-delay = <0>;

			thermal-sensors = <&tmu 0>;



			cooling-maps {

				map0 {

				     /* Corresponds to 800MHz at freq_table */

				     cooling-device = <&cpu0 9 9>;

				};

				map1 {

				     /* Corresponds to 200MHz at freq_table */

				     cooling-device = <&cpu0 15 15>;

			       };

		       };

		};

	};



		sata: sata@122F0000 {

			compatible = "snps,dwc-ahci";

			samsung,sata-freq = <66>;
@@ -328,62 +302,7 @@ 
			status = "disabled";

		};



	i2c_0: i2c@12C60000 {

		compatible = "samsung,s3c2440-i2c";

		reg = <0x12C60000 0x100>;

		interrupts = <0 56 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&clock CLK_I2C0>;

		clock-names = "i2c";

		pinctrl-names = "default";

		pinctrl-0 = <&i2c0_bus>;

		samsung,sysreg-phandle = <&sysreg_system_controller>;

		status = "disabled";

	};



	i2c_1: i2c@12C70000 {

		compatible = "samsung,s3c2440-i2c";

		reg = <0x12C70000 0x100>;

		interrupts = <0 57 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&clock CLK_I2C1>;

		clock-names = "i2c";

		pinctrl-names = "default";

		pinctrl-0 = <&i2c1_bus>;

		samsung,sysreg-phandle = <&sysreg_system_controller>;

		status = "disabled";

	};



	i2c_2: i2c@12C80000 {

		compatible = "samsung,s3c2440-i2c";

		reg = <0x12C80000 0x100>;

		interrupts = <0 58 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&clock CLK_I2C2>;

		clock-names = "i2c";

		pinctrl-names = "default";

		pinctrl-0 = <&i2c2_bus>;

		samsung,sysreg-phandle = <&sysreg_system_controller>;

		status = "disabled";

	};



	i2c_3: i2c@12C90000 {

		compatible = "samsung,s3c2440-i2c";

		reg = <0x12C90000 0x100>;

		interrupts = <0 59 0>;

		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&clock CLK_I2C3>;

		clock-names = "i2c";

		pinctrl-names = "default";

		pinctrl-0 = <&i2c3_bus>;

		samsung,sysreg-phandle = <&sysreg_system_controller>;

		status = "disabled";

	};



		/* i2c_0-3 are defined in exynos5.dtsi */

		i2c_4: i2c@12CA0000 {

			compatible = "samsung,s3c2440-i2c";

			reg = <0x12CA0000 0x100>;
@@ -662,15 +581,6 @@ 
			samsung,pmureg-phandle = <&pmu_system_controller>;

		};



	pwm: pwm@12dd0000 {

		compatible = "samsung,exynos4210-pwm";

		reg = <0x12dd0000 0x100>;

		samsung,pwm-outputs = <0>, <1>, <2>, <3>;

		#pwm-cells = <3>;

		clocks = <&clock CLK_PWM>;

		clock-names = "timers";

	};



		amba {

			#address-cells = <1>;

			#size-cells = <1>;
@@ -1055,6 +965,26 @@ 
		};

	};



	thermal-zones {

		cpu_thermal: cpu-thermal {

			polling-delay-passive = <0>;

			polling-delay = <0>;

			thermal-sensors = <&tmu 0>;



			cooling-maps {

				map0 {

				     /* Corresponds to 800MHz at freq_table */

				     cooling-device = <&cpu0 9 9>;

				};

				map1 {

				     /* Corresponds to 200MHz at freq_table */

				     cooling-device = <&cpu0 15 15>;

			       };

		       };

		};

	};

};



&dp {

	power-domains = <&pd_disp1>;

	clocks = <&clock CLK_DP>;
@@ -1070,6 +1000,39 @@ 
	iommus = <&sysmmu_fimd1>;

};



&i2c_0 {

	clocks = <&clock CLK_I2C0>;

	clock-names = "i2c";

	pinctrl-names = "default";

	pinctrl-0 = <&i2c0_bus>;

};



&i2c_1 {

	clocks = <&clock CLK_I2C1>;

	clock-names = "i2c";

	pinctrl-names = "default";

	pinctrl-0 = <&i2c1_bus>;

};



&i2c_2 {

	clocks = <&clock CLK_I2C2>;

	clock-names = "i2c";

	pinctrl-names = "default";

	pinctrl-0 = <&i2c2_bus>;

};



&i2c_3 {

	clocks = <&clock CLK_I2C3>;

	clock-names = "i2c";

	pinctrl-names = "default";

	pinctrl-0 = <&i2c3_bus>;

};



&pwm {

	clocks = <&clock CLK_PWM>;

	clock-names = "timers";

};



&rtc {

	clocks = <&clock CLK_RTC>;

	clock-names = "rtc";

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