Commit 95e395c8 authored by Alexandre Torgue's avatar Alexandre Torgue
Browse files

ARM: dts: stm32: Introduce new STM32MP15 SOCs: STM32MP151 and STM32MP153 

STM32MP151 and STM32MP153 were not explicitly supported through
stm32mp157c.dts. This commit adds dedicated files to support all STM32MP15
SOCs family.

The differences between those SOCs are:
 -STM32MP151 [1]: common file.
 -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU.
 -STM32MP157 [3]: STM32MP153 + DSI + GPU.

[1] https://www.st.com/resource/en/reference_manual/dm00366349.pdf
[2] https://www.st.com/resource/en/reference_manual/dm00366355.pdf
[3] https://www.st.com/resource/en/reference_manual/dm00327659.pdf



Signed-off-by: default avatarAlexandre Torgue <alexandre.torgue@st.com>
parent 48c7181f

arch/arm/boot/dts/stm32mp157c.dtsi→arch/arm/boot/dts/stm32mp151.dtsi

+0 −52
Original line number Diff line number Diff line
@@ -20,12 +20,6 @@ 
			device_type = "cpu";

			reg = <0>;

		};



		cpu1: cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

		};

	};



	psci {
@@ -953,32 +947,6 @@ 
			};

		};



		m_can1: can@4400e000 {

			compatible = "bosch,m_can";

			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;

			reg-names = "m_can", "message_ram";

			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "int0", "int1";

			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;

			clock-names = "hclk", "cclk";

			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;

			status = "disabled";

		};



		m_can2: can@4400f000 {

			compatible = "bosch,m_can";

			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;

			reg-names = "m_can", "message_ram";

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "int0", "int1";

			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;

			clock-names = "hclk", "cclk";

			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;

			status = "disabled";

		};



		dma1: dma@48000000 {

			compatible = "st,stm32-dma";

			reg = <0x48000000 0x400>;
@@ -1444,26 +1412,6 @@ 
			status = "disabled";

		};



		gpu: gpu@59000000 {

			compatible = "vivante,gc";

			reg = <0x59000000 0x800>;

			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc GPU>, <&rcc GPU_K>;

			clock-names = "bus" ,"core";

			resets = <&rcc GPU_R>;

			status = "disabled";

		};



		dsi: dsi@5a000000 {

			compatible = "st,stm32-dsi";

			reg = <0x5a000000 0x800>;

			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;

			clock-names = "pclk", "ref", "px_clk";

			resets = <&rcc DSI_R>;

			reset-names = "apb";

			status = "disabled";

		};



		ltdc: display-controller@5a001000 {

			compatible = "st,stm32-ltdc";

			reg = <0x5a001000 0x400>;

arch/arm/boot/dts/stm32mp153.dtsi

0 → 100644
+45 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved

 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.

 */



#include "stm32mp151.dtsi"



/ {

	cpus {

		cpu1: cpu@1 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

		};

	};



	soc {

		m_can1: can@4400e000 {

			compatible = "bosch,m_can";

			reg = <0x4400e000 0x400>, <0x44011000 0x1400>;

			reg-names = "m_can", "message_ram";

			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "int0", "int1";

			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;

			clock-names = "hclk", "cclk";

			bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;

			status = "disabled";

		};



		m_can2: can@4400f000 {

			compatible = "bosch,m_can";

			reg = <0x4400f000 0x400>, <0x44011000 0x2800>;

			reg-names = "m_can", "message_ram";

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "int0", "int1";

			clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;

			clock-names = "hclk", "cclk";

			bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/stm32mp157.dtsi

0 → 100644
+31 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)

/*

 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved

 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.

 */



#include "stm32mp153.dtsi"



/ {

	soc {

		gpu: gpu@59000000 {

			compatible = "vivante,gc";

			reg = <0x59000000 0x800>;

			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&rcc GPU>, <&rcc GPU_K>;

			clock-names = "bus" ,"core";

			resets = <&rcc GPU_R>;

			status = "disabled";

		};



		dsi: dsi@5a000000 {

			compatible = "st,stm32-dsi";

			reg = <0x5a000000 0x800>;

			clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;

			clock-names = "pclk", "ref", "px_clk";

			resets = <&rcc DSI_R>;

			reset-names = "apb";

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/stm32mp157a-avenger96.dts

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 


/dts-v1/;



#include "stm32mp157c.dtsi"

#include "stm32mp157.dtsi"

#include "stm32mp15-pinctrl.dtsi"

#include "stm32mp15xxac-pinctrl.dtsi"

#include <dt-bindings/gpio/gpio.h>

arch/arm/boot/dts/stm32mp157a-dk1.dts

+1 −1
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 


/dts-v1/;



#include "stm32mp157c.dtsi"

#include "stm32mp157.dtsi"

#include "stm32mp15-pinctrl.dtsi"

#include "stm32mp15xxac-pinctrl.dtsi"

#include <dt-bindings/gpio/gpio.h>

CRA Git | Maintained and supported by SUSTech CRA and CCSE