tools headers UAPI: Update tools's copy of drm.h headers

#else /* One of the BSDs */

#include <stdint.h>

#include <sys/ioccom.h>

#include <sys/types.h>

typedef int8_t   __s8;

struct i915_engine_class_instance {

	__u16 engine_class; /* see enum drm_i915_gem_engine_class */

	__u16 engine_instance;

#define I915_ENGINE_CLASS_INVALID_NONE -1

#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2

};

/**

#define DRM_I915_PERF_ADD_CONFIG	0x37

#define DRM_I915_PERF_REMOVE_CONFIG	0x38

#define DRM_I915_QUERY			0x39

#define DRM_I915_GEM_VM_CREATE		0x3a

#define DRM_I915_GEM_VM_DESTROY		0x3b

/* Must be kept compact -- no holes */

#define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

#define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)

#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)

#define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)

#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)

#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)

/* Allow drivers to submit batchbuffers directly to hardware, relying

 * on the security mechanisms provided by hardware.

 */

#define I915_PARAM_MMAP_GTT_COHERENT	52

/*

 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel

 * execution through use of explicit fence support.

 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.

 */

#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53

/* Must be kept compact -- no holes and well documented */

typedef struct drm_i915_getparam {

 */

#define I915_EXEC_FENCE_ARRAY   (1<<19)

#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_ARRAY<<1))

/*

 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent

 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing

 * the batch.

 *

 * Returns -EINVAL if the sync_file fd cannot be found.

 */

#define I915_EXEC_FENCE_SUBMIT		(1 << 20)

#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))

#define I915_EXEC_CONTEXT_ID_MASK	(0xffffffff)

#define i915_execbuffer2_set_context_id(eb2, context) \

	__u32 ctx_id; /* output: id of new context*/

	__u32 flags;

#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS	(1u << 0)

#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE	(1u << 1)

#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \

	(-(I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS << 1))

	(-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))

	__u64 extensions;

};

 * On creation, all new contexts are marked as recoverable.

 */

#define I915_CONTEXT_PARAM_RECOVERABLE	0x8

	/*

	 * The id of the associated virtual memory address space (ppGTT) of

	 * this context. Can be retrieved and passed to another context

	 * (on the same fd) for both to use the same ppGTT and so share

	 * address layouts, and avoid reloading the page tables on context

	 * switches between themselves.

	 *

	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.

	 */

#define I915_CONTEXT_PARAM_VM		0x9

/*

 * I915_CONTEXT_PARAM_ENGINES:

 *

 * Bind this context to operate on this subset of available engines. Henceforth,

 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as

 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]

 * and upwards. Slots 0...N are filled in using the specified (class, instance).

 * Use

 *	engine_class: I915_ENGINE_CLASS_INVALID,

 *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE

 * to specify a gap in the array that can be filled in later, e.g. by a

 * virtual engine used for load balancing.

 *

 * Setting the number of engines bound to the context to 0, by passing a zero

 * sized argument, will revert back to default settings.

 *

 * See struct i915_context_param_engines.

 *

 * Extensions:

 *   i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)

 *   i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)

 */

#define I915_CONTEXT_PARAM_ENGINES	0xa

/* Must be kept compact -- no holes and well documented */

	__u64 value;

	struct i915_engine_class_instance engine;

	/*

	 * Unused for now. Must be cleared to zero.

	 * Unknown flags must be cleared to zero.

	 */

	__u32 flags;

#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)

	/*

	 * Mask of slices to enable for the context. Valid values are a subset

	__u32 rsvd;

};

/*

 * i915_context_engines_load_balance:

 *

 * Enable load balancing across this set of engines.

 *

 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when

 * used will proxy the execbuffer request onto one of the set of engines

 * in such a way as to distribute the load evenly across the set.

 *

 * The set of engines must be compatible (e.g. the same HW class) as they

 * will share the same logical GPU context and ring.

 *

 * To intermix rendering with the virtual engine and direct rendering onto

 * the backing engines (bypassing the load balancing proxy), the context must

 * be defined to use a single timeline for all engines.

 */

struct i915_context_engines_load_balance {

	struct i915_user_extension base;

	__u16 engine_index;

	__u16 num_siblings;

	__u32 flags; /* all undefined flags must be zero */

	__u64 mbz64; /* reserved for future use; must be zero */

	struct i915_engine_class_instance engines[0];

} __attribute__((packed));

#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \

	struct i915_user_extension base; \

	__u16 engine_index; \

	__u16 num_siblings; \

	__u32 flags; \

	__u64 mbz64; \

	struct i915_engine_class_instance engines[N__]; \

} __attribute__((packed)) name__

/*

 * i915_context_engines_bond:

 *

 * Constructed bonded pairs for execution within a virtual engine.

 *

 * All engines are equal, but some are more equal than others. Given

 * the distribution of resources in the HW, it may be preferable to run

 * a request on a given subset of engines in parallel to a request on a

 * specific engine. We enable this selection of engines within a virtual

 * engine by specifying bonding pairs, for any given master engine we will

 * only execute on one of the corresponding siblings within the virtual engine.

 *

 * To execute a request in parallel on the master engine and a sibling requires

 * coordination with a I915_EXEC_FENCE_SUBMIT.

 */

struct i915_context_engines_bond {

	struct i915_user_extension base;

	struct i915_engine_class_instance master;

	__u16 virtual_index; /* index of virtual engine in ctx->engines[] */

	__u16 num_bonds;

	__u64 flags; /* all undefined flags must be zero */

	__u64 mbz64[4]; /* reserved for future use; must be zero */

	struct i915_engine_class_instance engines[0];

} __attribute__((packed));

#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \

	struct i915_user_extension base; \

	struct i915_engine_class_instance master; \

	__u16 virtual_index; \

	__u16 num_bonds; \

	__u64 flags; \

	__u64 mbz64[4]; \

	struct i915_engine_class_instance engines[N__]; \

} __attribute__((packed)) name__

struct i915_context_param_engines {

	__u64 extensions; /* linked chain of extension blocks, 0 terminates */

#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */

#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */

	struct i915_engine_class_instance engines[0];

} __attribute__((packed));

#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \

	__u64 extensions; \

	struct i915_engine_class_instance engines[N__]; \

} __attribute__((packed)) name__

struct drm_i915_gem_context_create_ext_setparam {

#define I915_CONTEXT_CREATE_EXT_SETPARAM 0

	struct i915_user_extension base;

	struct drm_i915_gem_context_param param;

};

struct drm_i915_gem_context_create_ext_clone {

#define I915_CONTEXT_CREATE_EXT_CLONE 1

	struct i915_user_extension base;

	__u32 clone_id;

	__u32 flags;

#define I915_CONTEXT_CLONE_ENGINES	(1u << 0)

#define I915_CONTEXT_CLONE_FLAGS	(1u << 1)

#define I915_CONTEXT_CLONE_SCHEDATTR	(1u << 2)

#define I915_CONTEXT_CLONE_SSEU		(1u << 3)

#define I915_CONTEXT_CLONE_TIMELINE	(1u << 4)

#define I915_CONTEXT_CLONE_VM		(1u << 5)

#define I915_CONTEXT_CLONE_UNKNOWN -(I915_CONTEXT_CLONE_VM << 1)

	__u64 rsvd;

};

struct drm_i915_gem_context_destroy {

	__u32 ctx_id;

	__u32 pad;

struct drm_i915_query_item {

	__u64 query_id;

#define DRM_I915_QUERY_TOPOLOGY_INFO    1

#define DRM_I915_QUERY_ENGINE_INFO	2

/* Must be kept compact -- no holes and well documented */

	/*

	__u8 data[];

};

/**

 * struct drm_i915_engine_info

 *

 * Describes one engine and it's capabilities as known to the driver.

 */

struct drm_i915_engine_info {

	/** Engine class and instance. */

	struct i915_engine_class_instance engine;

	/** Reserved field. */

	__u32 rsvd0;

	/** Engine flags. */

	__u64 flags;

	/** Capabilities of this engine. */

	__u64 capabilities;

#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)

#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)

	/** Reserved fields. */

	__u64 rsvd1[4];

};

/**

 * struct drm_i915_query_engine_info

 *

 * Engine info query enumerates all engines known to the driver by filling in

 * an array of struct drm_i915_engine_info structures.

 */

struct drm_i915_query_engine_info {

	/** Number of struct drm_i915_engine_info structs following. */

	__u32 num_engines;

	/** MBZ */

	__u32 rsvd[3];

	/** Marker for drm_i915_engine_info structures. */

	struct drm_i915_engine_info engines[];

};

#if defined(__cplusplus)

}

#endif