Commit 95c5824f authored by Pawan Gupta's avatar Pawan Gupta Committed by Thomas Gleixner
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x86/cpu: Add a "tsx=" cmdline option with TSX disabled by default



Add a kernel cmdline parameter "tsx" to control the Transactional
Synchronization Extensions (TSX) feature. On CPUs that support TSX
control, use "tsx=on|off" to enable or disable TSX. Not specifying this
option is equivalent to "tsx=off". This is because on certain processors
TSX may be used as a part of a speculative side channel attack.

Carve out the TSX controlling functionality into a separate compilation
unit because TSX is a CPU feature while the TSX async abort control
machinery will go to cpu/bugs.c.

 [ bp: - Massage, shorten and clear the arg buffer.
       - Clarifications of the tsx= possible options - Josh.
       - Expand on TSX_CTRL availability - Pawan. ]

Signed-off-by: default avatarPawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarJosh Poimboeuf <jpoimboe@redhat.com>
parent 286836a7
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+26 −0
Original line number Diff line number Diff line
@@ -4848,6 +4848,32 @@
			interruptions from clocksource watchdog are not
			acceptable).

	tsx=		[X86] Control Transactional Synchronization
			Extensions (TSX) feature in Intel processors that
			support TSX control.

			This parameter controls the TSX feature. The options are:

			on	- Enable TSX on the system. Although there are
				mitigations for all known security vulnerabilities,
				TSX has been known to be an accelerator for
				several previous speculation-related CVEs, and
				so there may be unknown	security risks associated
				with leaving it enabled.

			off	- Disable TSX on the system. (Note that this
				option takes effect only on newer CPUs which are
				not vulnerable to MDS, i.e., have
				MSR_IA32_ARCH_CAPABILITIES.MDS_NO=1 and which get
				the new IA32_TSX_CTRL MSR through a microcode
				update. This new MSR allows for the reliable
				deactivation of the TSX functionality.)

			Not specifying this option is equivalent to tsx=off.

			See Documentation/admin-guide/hw-vuln/tsx_async_abort.rst
			for more details.

	turbografx.map[2|3]=	[HW,JOY]
			TurboGraFX parallel port interface
			Format:
+1 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o

ifdef CONFIG_CPU_SUP_INTEL
obj-y			+= intel.o intel_pconfig.o
obj-y			+= intel.o intel_pconfig.o tsx.o
obj-$(CONFIG_PM)	+= intel_epb.o
endif
obj-$(CONFIG_CPU_SUP_AMD)		+= amd.o
+2 −0
Original line number Diff line number Diff line
@@ -1561,6 +1561,8 @@ void __init identify_boot_cpu(void)
#endif
	cpu_detect_tlb(&boot_cpu_data);
	setup_cr_pinning();

	tsx_init();
}

void identify_secondary_cpu(struct cpuinfo_x86 *c)
+16 −0
Original line number Diff line number Diff line
@@ -44,6 +44,22 @@ struct _tlb_table {
extern const struct cpu_dev *const __x86_cpu_dev_start[],
			    *const __x86_cpu_dev_end[];

#ifdef CONFIG_CPU_SUP_INTEL
enum tsx_ctrl_states {
	TSX_CTRL_ENABLE,
	TSX_CTRL_DISABLE,
	TSX_CTRL_NOT_SUPPORTED,
};

extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;

extern void __init tsx_init(void);
extern void tsx_enable(void);
extern void tsx_disable(void);
#else
static inline void tsx_init(void) { }
#endif /* CONFIG_CPU_SUP_INTEL */

extern void get_cpu_cap(struct cpuinfo_x86 *c);
extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
+5 −0
Original line number Diff line number Diff line
@@ -762,6 +762,11 @@ static void init_intel(struct cpuinfo_x86 *c)
		detect_tme(c);

	init_intel_misc_features(c);

	if (tsx_ctrl_state == TSX_CTRL_ENABLE)
		tsx_enable();
	if (tsx_ctrl_state == TSX_CTRL_DISABLE)
		tsx_disable();
}

#ifdef CONFIG_X86_32
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