Commit 95b80e0a authored by Thomas Petazzoni's avatar Thomas Petazzoni Committed by Jason Cooper
Browse files

arm: mach-mv78xx0: convert to use the mvebu-mbus driver 



This commit convers the mach-mv78xx0 sub-architecture to use the
mvebu-mbus driver. We simply have to call mvebu_mbus_init() in the
->init_early() function, and modify the PCIe code so that it uses the
new functions provided by mvebu-mbus to create the needed PCIe
windows.

Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 5d1190ea

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -588,6 +588,7 @@ config ARCH_MV78XX0 
	select GENERIC_CLOCKEVENTS

	select PCI

	select PLAT_ORION_LEGACY

	select MVEBU_MBUS

	help

	  Support for the following Marvell MV78xx0 series SoCs:

	  MV781x0, MV782x0.

arch/arm/mach-mv78xx0/Makefile

+1 −1
Original line number Diff line number Diff line 
obj-y				+= common.o addr-map.o mpp.o irq.o pcie.o

obj-y				+= common.o mpp.o irq.o pcie.o

obj-$(CONFIG_MACH_DB78X00_BP)	+= db78x00-bp-setup.o

obj-$(CONFIG_MACH_RD78X00_MASA)	+= rd78x00-masa-setup.o

obj-$(CONFIG_MACH_TERASTATION_WXL) += buffalo-wxl-setup.o

arch/arm/mach-mv78xx0/addr-map.c

deleted100644 → 0
+0 −93
Original line number Diff line number Diff line 
/*

 * arch/arm/mach-mv78xx0/addr-map.c

 *

 * Address map functions for Marvell MV78xx0 SoCs

 *

 * This file is licensed under the terms of the GNU General Public

 * License version 2.  This program is licensed "as is" without any

 * warranty of any kind, whether express or implied.

 */



#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/mbus.h>

#include <linux/io.h>

#include <plat/addr-map.h>

#include <mach/mv78xx0.h>

#include "common.h"



/*

 * Generic Address Decode Windows bit settings

 */

#define TARGET_DEV_BUS		1

#define TARGET_PCIE0		4

#define TARGET_PCIE1		8

#define TARGET_PCIE(i)		((i) ? TARGET_PCIE1 : TARGET_PCIE0)

#define ATTR_DEV_SPI_ROM	0x1f

#define ATTR_DEV_BOOT		0x2f

#define ATTR_DEV_CS3		0x37

#define ATTR_DEV_CS2		0x3b

#define ATTR_DEV_CS1		0x3d

#define ATTR_DEV_CS0		0x3e

#define ATTR_PCIE_IO(l)		(0xf0 & ~(0x10 << (l)))

#define ATTR_PCIE_MEM(l)	(0xf8 & ~(0x10 << (l)))



/*

 * CPU Address Decode Windows registers

 */

#define WIN0_OFF(n)		(BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))

#define WIN8_OFF(n)		(BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))



static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)

{

	/*

	 * Find the control register base address for this window.

	 *

	 * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)

	 * MBUS bridge depending on which CPU core we're running on,

	 * so we don't need to take that into account here.

	 */



	return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);

}



/*

 * Description of the windows needed by the platform code

 */

static struct orion_addr_map_cfg addr_map_cfg __initdata = {

	.num_wins = 14,

	.remappable_wins = 8,

	.win_cfg_base = win_cfg_base,

};



void __init mv78xx0_setup_cpu_mbus(void)

{

	/*

	 * Disable, clear and configure windows.

	 */

	orion_config_wins(&addr_map_cfg, NULL);



	/*

	 * Setup MBUS dram target info.

	 */

	if (mv78xx0_core_index() == 0)

		orion_setup_cpu_mbus_target(&addr_map_cfg,

					    (void __iomem *) DDR_WINDOW_CPU0_BASE);

	else

		orion_setup_cpu_mbus_target(&addr_map_cfg,

					    (void __iomem *) DDR_WINDOW_CPU1_BASE);

}



void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,

				      int maj, int min)

{

	orion_setup_cpu_win(&addr_map_cfg, window, base, size,

			    TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);

}



void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,

				       int maj, int min)

{

	orion_setup_cpu_win(&addr_map_cfg, window, base, size,

			    TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);

}

arch/arm/mach-mv78xx0/common.c

+8 −2
Original line number Diff line number Diff line
@@ -334,6 +334,14 @@ void __init mv78xx0_uart3_init(void) 
void __init mv78xx0_init_early(void)

{

	orion_time_set_base(TIMER_VIRT_BASE);

	if (mv78xx0_core_index() == 0)

		mvebu_mbus_init("marvell,mv78xx0-mbus",

				BRIDGE_WINS_CPU0_BASE, BRIDGE_WINS_SZ,

				DDR_WINDOW_CPU0_BASE, DDR_WINDOW_CPU_SZ);

	else

		mvebu_mbus_init("marvell,mv78xx0-mbus",

				BRIDGE_WINS_CPU1_BASE, BRIDGE_WINS_SZ,

				DDR_WINDOW_CPU1_BASE, DDR_WINDOW_CPU_SZ);

}



void __init_refok mv78xx0_timer_init(void)
@@ -397,8 +405,6 @@ void __init mv78xx0_init(void) 
	printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);

	printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);



	mv78xx0_setup_cpu_mbus();



#ifdef CONFIG_CACHE_FEROCEON_L2

	feroceon_l2_init(is_l2_writethrough());

#endif

arch/arm/mach-mv78xx0/include/mach/mv78xx0.h

+7 −2
Original line number Diff line number Diff line
@@ -60,13 +60,18 @@ 
 */

#define BRIDGE_VIRT_BASE	(MV78XX0_CORE_REGS_VIRT_BASE)

#define BRIDGE_PHYS_BASE	(MV78XX0_CORE_REGS_PHYS_BASE)

#define  BRIDGE_WINS_CPU0_BASE  (MV78XX0_CORE0_REGS_PHYS_BASE)

#define  BRIDGE_WINS_CPU1_BASE  (MV78XX0_CORE1_REGS_PHYS_BASE)

#define  BRIDGE_WINS_SZ         (0xA000)



/*

 * Register Map

 */

#define DDR_VIRT_BASE		(MV78XX0_REGS_VIRT_BASE + 0x00000)

#define  DDR_WINDOW_CPU0_BASE	(DDR_VIRT_BASE + 0x1500)

#define  DDR_WINDOW_CPU1_BASE	(DDR_VIRT_BASE + 0x1570)

#define DDR_PHYS_BASE           (MV78XX0_REGS_PHYS_BASE + 0x00000)

#define  DDR_WINDOW_CPU0_BASE	(DDR_PHYS_BASE + 0x1500)

#define  DDR_WINDOW_CPU1_BASE	(DDR_PHYS_BASE + 0x1570)

#define  DDR_WINDOW_CPU_SZ      (0x20)



#define DEV_BUS_PHYS_BASE	(MV78XX0_REGS_PHYS_BASE + 0x10000)

#define DEV_BUS_VIRT_BASE	(MV78XX0_REGS_VIRT_BASE + 0x10000)

CRA Git | Maintained and supported by SUSTech CRA and CCSE