Commit 9597f403 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: initialize platform caps in hwmgr_init. 



Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5141e9d2

drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c

+0 −34
Original line number Diff line number Diff line
@@ -24,8 +24,6 @@ 
#include "hwmgr.h"

#include "hardwaremanager.h"

#include "power_state.h"

#include "pp_acpi.h"

#include "amd_acpi.h"

#include "pp_debug.h"



#define PHM_FUNC_CHECK(hw) \
@@ -34,38 +32,6 @@ 
			return -EINVAL;				\

	} while (0)



void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)

{

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);



	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&

		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))

		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);

}



bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr)

{

	return hwmgr->block_hw_access;

drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c

+86 −23
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ 
#include "pp_debug.h"

#include "ppatomctrl.h"

#include "ppsmc.h"

#include "pp_acpi.h"

#include "amd_acpi.h"



#define VOLTAGE_SCALE               4
@@ -41,24 +43,8 @@ extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr); 
extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);

extern int iceland_hwmgr_init(struct pp_hwmgr *hwmgr);



static int hwmgr_set_features_platform_caps(struct pp_hwmgr *hwmgr)

{

	if (amdgpu_sclk_deep_sleep_en)

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_SclkDeepSleep);

	else

		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_SclkDeepSleep);



	if (amdgpu_powercontainment)

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			    PHM_PlatformCaps_PowerContainment);

	else

		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

			    PHM_PlatformCaps_PowerContainment);



	return 0;

}

static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);

static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);



int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle)

{
@@ -79,7 +65,8 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) 
	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;

	hwmgr->power_source = PP_PowerSource_AC;



	hwmgr_set_features_platform_caps(hwmgr);

	hwmgr_init_default_caps(hwmgr);

	hwmgr_set_user_specify_caps(hwmgr);



	switch (hwmgr->chip_family) {

	case AMDGPU_FAMILY_CZ:
@@ -108,8 +95,6 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) 
		return -EINVAL;

	}



	phm_init_dynamic_caps(hwmgr);



	return 0;

}
@@ -217,8 +202,6 @@ int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index, 
}









/**

 * Returns once the part of the register indicated by the mask has

 * reached the given value.The indirect space is described by giving
@@ -613,3 +596,83 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) 
	printk(KERN_ERR "DAL requested level can not"

			" found a available voltage in VDDC DPM Table \n");

}



void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)

{

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableVoltageTransition);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableEngineTransition);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMemoryTransition);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGClockGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMGCGTSSM);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLSClockGating);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Force3DClockSupport);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableLightSleep);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableMCLS);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisablePowerGating);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableDPM);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DisableSMUUVDHandshake);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ThermalAutoThrottling);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_NoOD5Support);

	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UserMaxClockForMultiDisplays);



	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);

	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);



	if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&

		acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))

		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

		PHM_PlatformCaps_DynamicPatchPowerState);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			 PHM_PlatformCaps_TablelessHardwareInterface);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

		PHM_PlatformCaps_EnableSMU7ThermalManagement);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_DynamicPowerManagement);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_UnTabledHardwareInterface);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

					PHM_PlatformCaps_SMC);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

					PHM_PlatformCaps_DynamicUVDState);



	phm_cap_set(hwmgr->platform_descriptor.platformCaps,

						PHM_PlatformCaps_FanSpeedInTableIsRPM);



	return;

}



int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)

{

	if (amdgpu_sclk_deep_sleep_en)

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_SclkDeepSleep);

	else

		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

			PHM_PlatformCaps_SclkDeepSleep);



	if (amdgpu_powercontainment)

		phm_cap_set(hwmgr->platform_descriptor.platformCaps,

			    PHM_PlatformCaps_PowerContainment);

	else

		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,

			    PHM_PlatformCaps_PowerContainment);



	hwmgr->feature_mask = amdgpu_pp_feature_mask;



	return 0;

}

drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h

+0 −1
Original line number Diff line number Diff line
@@ -341,7 +341,6 @@ extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr); 
extern int phm_setup_asic(struct pp_hwmgr *hwmgr);

extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);

extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);

extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);

extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);

extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);

extern int phm_set_power_state(struct pp_hwmgr *hwmgr,

drivers/gpu/drm/amd/powerplay/inc/hwmgr.h

+1 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ struct pp_atomctrl_voltage_table; 


extern int amdgpu_powercontainment;

extern int amdgpu_sclk_deep_sleep_en;

extern unsigned amdgpu_pp_feature_mask;



enum DISPLAY_GAP {

	DISPLAY_GAP_VBLANK_OR_WM = 0,   /* Wait for vblank or MCHG watermark. */

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