Commit 9596017e authored by Adrian Bunk's avatar Adrian Bunk Committed by Linus Torvalds
Browse files

x86: remove support for the Rise CPU 



The Rise CPUs were only very short-lived, and there are no reports of
anyone both owning one and running Linux on it.

Googling for the printk string "CPU: Rise iDragon" didn't find any dmesg
available online.

If it turns out that against all expectations there are actually users
reverting this patch would be easy.

This patch will make the kernel images smaller by a few bytes for all
i386 users.

Signed-off-by: default avatarAdrian Bunk <bunk@stusta.de>
Acked-by: default avatarDave Jones <davej@redhat.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent ef3e28c5

arch/i386/kernel/cpu/Makefile

+0 −1
Original line number Diff line number Diff line
@@ -9,7 +9,6 @@ obj-y += cyrix.o 
obj-y	+=	centaur.o

obj-y	+=	transmeta.o

obj-y	+=	intel.o intel_cacheinfo.o addon_cpuid_features.o

obj-y	+=	rise.o

obj-y	+=	nexgen.o

obj-y	+=	umc.o

arch/i386/kernel/cpu/common.c

+0 −2
Original line number Diff line number Diff line
@@ -606,7 +606,6 @@ extern int nsc_init_cpu(void); 
extern int amd_init_cpu(void);

extern int centaur_init_cpu(void);

extern int transmeta_init_cpu(void);

extern int rise_init_cpu(void);

extern int nexgen_init_cpu(void);

extern int umc_init_cpu(void);
@@ -618,7 +617,6 @@ void __init early_cpu_init(void) 
	amd_init_cpu();

	centaur_init_cpu();

	transmeta_init_cpu();

	rise_init_cpu();

	nexgen_init_cpu();

	umc_init_cpu();

	early_cpu_detect();

arch/i386/kernel/cpu/rise.c

deleted100644 → 0
+0 −52
Original line number Diff line number Diff line 
#include <linux/kernel.h>

#include <linux/init.h>

#include <linux/bitops.h>

#include <asm/processor.h>



#include "cpu.h"



static void __cpuinit init_rise(struct cpuinfo_x86 *c)

{

	printk("CPU: Rise iDragon");

	if (c->x86_model > 2)

		printk(" II");

	printk("\n");



	/* Unhide possibly hidden capability flags

	   The mp6 iDragon family don't have MSRs.

	   We switch on extra features with this cpuid weirdness: */

	__asm__ (

		"movl $0x6363452a, %%eax\n\t"

		"movl $0x3231206c, %%ecx\n\t"

		"movl $0x2a32313a, %%edx\n\t"

		"cpuid\n\t"

		"movl $0x63634523, %%eax\n\t"

		"movl $0x32315f6c, %%ecx\n\t"

		"movl $0x2333313a, %%edx\n\t"

		"cpuid\n\t" : : : "eax", "ebx", "ecx", "edx"

	);

	set_bit(X86_FEATURE_CX8, c->x86_capability);

}



static struct cpu_dev rise_cpu_dev __cpuinitdata = {

	.c_vendor	= "Rise",

	.c_ident	= { "RiseRiseRise" },

	.c_models = {

		{ .vendor = X86_VENDOR_RISE, .family = 5, .model_names = 

		  { 

			  [0] = "iDragon", 

			  [2] = "iDragon", 

			  [8] = "iDragon II", 

			  [9] = "iDragon II"

		  }

		},

	},

	.c_init		= init_rise,

};



int __init rise_init_cpu(void)

{

	cpu_devs[X86_VENDOR_RISE] = &rise_cpu_dev;

	return 0;

}

include/asm-i386/processor.h

+0 −1
Original line number Diff line number Diff line
@@ -88,7 +88,6 @@ struct cpuinfo_x86 { 
#define X86_VENDOR_UMC 3

#define X86_VENDOR_NEXGEN 4

#define X86_VENDOR_CENTAUR 5

#define X86_VENDOR_RISE 6

#define X86_VENDOR_TRANSMETA 7

#define X86_VENDOR_NSC 8

#define X86_VENDOR_NUM 9

include/asm-x86_64/processor.h

+0 −1
Original line number Diff line number Diff line
@@ -83,7 +83,6 @@ struct cpuinfo_x86 { 
#define X86_VENDOR_UMC 3

#define X86_VENDOR_NEXGEN 4

#define X86_VENDOR_CENTAUR 5

#define X86_VENDOR_RISE 6

#define X86_VENDOR_TRANSMETA 7

#define X86_VENDOR_NUM 8

#define X86_VENDOR_UNKNOWN 0xff

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