Commit 958e052c authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'usb-for-v4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next 

Felipe writes:

usb: changes for v4.16 merge window

Not many changes here, the most important being an improvement for TI's
AM57xx and DRA7xx devices which allows them to disable a metastability
workaround in situations where we know what's going on.

Other than that, we have a set of changes on Renesas UDC to make the
code a little easier to read and maintain while also better supporting
extcon framework.

The u_serial adaptation layer learned to use kfifo instead of cooking
its own FIFO implementation.

DWC3 learned to decode a few more USB requests on the trace output.
parents f7a5d7b3 8ada211d

Documentation/devicetree/bindings/usb/dwc3.txt

+2 −0
Original line number Diff line number Diff line
@@ -47,6 +47,8 @@ Optional properties: 
			from P0 to P1/P2/P3 without delay.

 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check

			during HS transmit.

 - snps,dis_metastability_quirk: when set, disable metastability workaround.

			CAUTION: use only if you are absolutely sure of it.

 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal

			utmi_l1_suspend_n, false when asserts utmi_sleep_n

 - snps,hird-threshold: HIRD threshold

drivers/usb/dwc2/core.h

+2 −0
Original line number Diff line number Diff line
@@ -929,6 +929,7 @@ struct dwc2_hsotg { 
	int     irq;

	struct clk *clk;

	struct reset_control *reset;

	struct reset_control *reset_ecc;



	unsigned int queuing_high_bandwidth:1;

	unsigned int srp_success:1;
@@ -971,6 +972,7 @@ struct dwc2_hsotg { 
	} flags;



	struct list_head non_periodic_sched_inactive;

	struct list_head non_periodic_sched_waiting;

	struct list_head non_periodic_sched_active;

	struct list_head *non_periodic_qh_ptr;

	struct list_head periodic_sched_inactive;

drivers/usb/dwc2/hcd.c

+7 −0
Original line number Diff line number Diff line
@@ -659,6 +659,10 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, 
	list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,

			    qh_list_entry)

		dev_dbg(hsotg->dev, "    %p\n", qh);

	dev_dbg(hsotg->dev, "  NP waiting sched:\n");

	list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,

			    qh_list_entry)

		dev_dbg(hsotg->dev, "    %p\n", qh);

	dev_dbg(hsotg->dev, "  NP active sched:\n");

	list_for_each_entry(qh, &hsotg->non_periodic_sched_active,

			    qh_list_entry)
@@ -1818,6 +1822,7 @@ static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg, 
static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)

{

	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);

	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);

	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);

	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);

	dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
@@ -4998,6 +5003,7 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) 


	/* Free memory for QH/QTD lists */

	dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);

	dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);

	dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);

	dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);

	dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
@@ -5159,6 +5165,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg) 


	/* Initialize the non-periodic schedule */

	INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);

	INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);

	INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);



	/* Initialize the periodic schedule */

drivers/usb/dwc2/hcd.h

+9 −0
Original line number Diff line number Diff line
@@ -314,12 +314,16 @@ struct dwc2_hs_transfer_time { 
 *                      descriptor and indicates original XferSize value for the

 *                      descriptor

 * @unreserve_timer:    Timer for releasing periodic reservation.

 * @wait_timer:         Timer used to wait before re-queuing.

 * @dwc2_tt:            Pointer to our tt info (or NULL if no tt).

 * @ttport:             Port number within our tt.

 * @tt_buffer_dirty     True if clear_tt_buffer_complete is pending

 * @unreserve_pending:  True if we planned to unreserve but haven't yet.

 * @schedule_low_speed: True if we have a low/full speed component (either the

 *			host is in low/full speed mode or do_split).

 * @want_wait:          We should wait before re-queuing; only matters for non-

 *                      periodic transfers and is ignored for periodic ones.

 * @wait_timer_cancel:  Set to true to cancel the wait_timer.

 *

 * A Queue Head (QH) holds the static characteristics of an endpoint and

 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may
@@ -354,11 +358,14 @@ struct dwc2_qh { 
	u32 desc_list_sz;

	u32 *n_bytes;

	struct timer_list unreserve_timer;

	struct timer_list wait_timer;

	struct dwc2_tt *dwc_tt;

	int ttport;

	unsigned tt_buffer_dirty:1;

	unsigned unreserve_pending:1;

	unsigned schedule_low_speed:1;

	unsigned want_wait:1;

	unsigned wait_timer_cancel:1;

};



/**
@@ -389,6 +396,7 @@ struct dwc2_qh { 
 * @n_desc:             Number of DMA descriptors for this QTD

 * @isoc_frame_index_last: Last activated frame (packet) index, used in

 *                      descriptor DMA mode only

 * @num_naks:           Number of NAKs received on this QTD.

 * @urb:                URB for this transfer

 * @qh:                 Queue head for this QTD

 * @qtd_list_entry:     For linking to the QH's list of QTDs
@@ -419,6 +427,7 @@ struct dwc2_qtd { 
	u8 error_count;

	u8 n_desc;

	u16 isoc_frame_index_last;

	u16 num_naks;

	struct dwc2_hcd_urb *urb;

	struct dwc2_qh *qh;

	struct list_head qtd_list_entry;

drivers/usb/dwc2/hcd_intr.c

+20 −0
Original line number Diff line number Diff line
@@ -53,6 +53,12 @@ 
#include "core.h"

#include "hcd.h"



/*

 * If we get this many NAKs on a split transaction we'll slow down

 * retransmission.  A 1 here means delay after the first NAK.

 */

#define DWC2_NAKS_BEFORE_DELAY		3



/* This function is for debug only */

static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)

{
@@ -1201,11 +1207,25 @@ static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg, 
	/*

	 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and

	 * interrupt. Re-start the SSPLIT transfer.

	 *

	 * Normally for non-periodic transfers we'll retry right away, but to

	 * avoid interrupt storms we'll wait before retrying if we've got

	 * several NAKs. If we didn't do this we'd retry directly from the

	 * interrupt handler and could end up quickly getting another

	 * interrupt (another NAK), which we'd retry.

	 *

	 * Note that in DMA mode software only gets involved to re-send NAKed

	 * transfers for split transactions, so we only need to apply this

	 * delaying logic when handling splits. In non-DMA mode presumably we

	 * might want a similar delay if someone can demonstrate this problem

	 * affects that code path too.

	 */

	if (chan->do_split) {

		if (chan->complete_split)

			qtd->error_count = 0;

		qtd->complete_split = 0;

		qtd->num_naks++;

		qtd->qh->want_wait = qtd->num_naks >= DWC2_NAKS_BEFORE_DELAY;

		dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);

		goto handle_nak_done;

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE