drm/i915/perf: enable perf support on CNL (95690a02) · Commits · 戴 / test

drivers/gpu/drm/i915/Makefile

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -163,7 +163,8 @@ i915-y += i915_perf.o \
	i915_oa_kblgt3.o \		i915_oa_kblgt3.o \
	i915_oa_glk.o \		i915_oa_glk.o \
	i915_oa_cflgt2.o \		i915_oa_cflgt2.o \
	i915_oa_cflgt3.o		i915_oa_cflgt3.o \
			i915_oa_cnl.o

	ifeq ($(CONFIG_DRM_I915_GVT),y)		ifeq ($(CONFIG_DRM_I915_GVT),y)
	i915-y += intel_gvt.o		i915-y += intel_gvt.o

drivers/gpu/drm/i915/i915_oa_cnl.c

0 → 100644

+121 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Autogenerated file by GPU Top : https://github.com/rib/gputop
			* DO NOT EDIT manually!
			*
			*
			* Copyright (c) 2015 Intel Corporation
			*
			* Permission is hereby granted, free of charge, to any person obtaining a
			* copy of this software and associated documentation files (the "Software"),
			* to deal in the Software without restriction, including without limitation
			* the rights to use, copy, modify, merge, publish, distribute, sublicense,
			* and/or sell copies of the Software, and to permit persons to whom the
			* Software is furnished to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice (including the next
			* paragraph) shall be included in all copies or substantial portions of the
			* Software.
			*
			* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
			* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
			* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
			* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
			* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
			* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
			* IN THE SOFTWARE.
			*
			*/

			#include <linux/sysfs.h>

			#include "i915_drv.h"
			#include "i915_oa_cnl.h"

			static const struct i915_oa_reg b_counter_config_test_oa[] = {
			{ _MMIO(0x2740), 0x00000000 },
			{ _MMIO(0x2710), 0x00000000 },
			{ _MMIO(0x2714), 0xf0800000 },
			{ _MMIO(0x2720), 0x00000000 },
			{ _MMIO(0x2724), 0xf0800000 },
			{ _MMIO(0x2770), 0x00000004 },
			{ _MMIO(0x2774), 0x0000ffff },
			{ _MMIO(0x2778), 0x00000003 },
			{ _MMIO(0x277c), 0x0000ffff },
			{ _MMIO(0x2780), 0x00000007 },
			{ _MMIO(0x2784), 0x0000ffff },
			{ _MMIO(0x2788), 0x00100002 },
			{ _MMIO(0x278c), 0x0000fff7 },
			{ _MMIO(0x2790), 0x00100002 },
			{ _MMIO(0x2794), 0x0000ffcf },
			{ _MMIO(0x2798), 0x00100082 },
			{ _MMIO(0x279c), 0x0000ffef },
			{ _MMIO(0x27a0), 0x001000c2 },
			{ _MMIO(0x27a4), 0x0000ffe7 },
			{ _MMIO(0x27a8), 0x00100001 },
			{ _MMIO(0x27ac), 0x0000ffe7 },
			};

			static const struct i915_oa_reg flex_eu_config_test_oa[] = {
			};

			static const struct i915_oa_reg mux_config_test_oa[] = {
			{ _MMIO(0xd04), 0x00000200 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x17060000 },
			{ _MMIO(0x9840), 0x00000000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x13034000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x07060066 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x05060000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x0f080040 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x07091000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x0f041000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x1d004000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x35000000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x49000000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x3d000000 },
			{ _MMIO(0x9884), 0x00000007 },
			{ _MMIO(0x9888), 0x31000000 },
			};

			static ssize_t
			show_test_oa_id(struct device kdev, struct device_attribute attr, char *buf)
			{
			return sprintf(buf, "1\n");
			}

			void
			i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv)
			{
			strncpy(dev_priv->perf.oa.test_config.uuid,
			"db41edd4-d8e7-4730-ad11-b9a2d6833503",
			UUID_STRING_LEN);
			dev_priv->perf.oa.test_config.id = 1;

			dev_priv->perf.oa.test_config.mux_regs = mux_config_test_oa;
			dev_priv->perf.oa.test_config.mux_regs_len = ARRAY_SIZE(mux_config_test_oa);

			dev_priv->perf.oa.test_config.b_counter_regs = b_counter_config_test_oa;
			dev_priv->perf.oa.test_config.b_counter_regs_len = ARRAY_SIZE(b_counter_config_test_oa);

			dev_priv->perf.oa.test_config.flex_regs = flex_eu_config_test_oa;
			dev_priv->perf.oa.test_config.flex_regs_len = ARRAY_SIZE(flex_eu_config_test_oa);

			dev_priv->perf.oa.test_config.sysfs_metric.name = "db41edd4-d8e7-4730-ad11-b9a2d6833503";
			dev_priv->perf.oa.test_config.sysfs_metric.attrs = dev_priv->perf.oa.test_config.attrs;

			dev_priv->perf.oa.test_config.attrs[0] = &dev_priv->perf.oa.test_config.sysfs_metric_id.attr;

			dev_priv->perf.oa.test_config.sysfs_metric_id.attr.name = "id";
			dev_priv->perf.oa.test_config.sysfs_metric_id.attr.mode = 0444;
			dev_priv->perf.oa.test_config.sysfs_metric_id.show = show_test_oa_id;
			}

drivers/gpu/drm/i915/i915_oa_cnl.h

0 → 100644

+34 −0

Original line number	Original line	Diff line number	Diff line
			/*
			* Autogenerated file by GPU Top : https://github.com/rib/gputop
			* DO NOT EDIT manually!
			*
			*
			* Copyright (c) 2015 Intel Corporation
			*
			* Permission is hereby granted, free of charge, to any person obtaining a
			* copy of this software and associated documentation files (the "Software"),
			* to deal in the Software without restriction, including without limitation
			* the rights to use, copy, modify, merge, publish, distribute, sublicense,
			* and/or sell copies of the Software, and to permit persons to whom the
			* Software is furnished to do so, subject to the following conditions:
			*
			* The above copyright notice and this permission notice (including the next
			* paragraph) shall be included in all copies or substantial portions of the
			* Software.
			*
			* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
			* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
			* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
			* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
			* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
			* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
			* IN THE SOFTWARE.
			*
			*/

			#ifndef __I915_OA_CNL_H__
			#define __I915_OA_CNL_H__

			extern void i915_perf_load_test_config_cnl(struct drm_i915_private *dev_priv);

			#endif

drivers/gpu/drm/i915/i915_perf.c

+40 −1

Original line number	Original line	Diff line number	Diff line
	@@ -208,6 +208,7 @@
	#include "i915_oa_glk.h"		#include "i915_oa_glk.h"
	#include "i915_oa_cflgt2.h"		#include "i915_oa_cflgt2.h"
	#include "i915_oa_cflgt3.h"		#include "i915_oa_cflgt3.h"
			#include "i915_oa_cnl.h"

	/* HW requires this to be a power of two, between 128k and 16M, though driver		/* HW requires this to be a power of two, between 128k and 16M, though driver
	* is currently generally designed assuming the largest 16M size is used such		* is currently generally designed assuming the largest 16M size is used such
	@@ -1852,7 +1853,7 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv,
	* be read back from automatically triggered reports, as part of the		* be read back from automatically triggered reports, as part of the
	* RPT_ID field.		* RPT_ID field.
	*/		*/
	if (IS_GEN9(dev_priv)) {		if (IS_GEN9(dev_priv) \|\| IS_GEN10(dev_priv)) {
	I915_WRITE(GEN8_OA_DEBUG,		I915_WRITE(GEN8_OA_DEBUG,
	_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS \|		_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS \|
	GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));		GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
	@@ -1885,6 +1886,16 @@ static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)

	}		}

			static void gen10_disable_metric_set(struct drm_i915_private *dev_priv)
			{
			/* Reset all contexts' slices/subslices configurations. */
			gen8_configure_all_contexts(dev_priv, NULL, false);

			/* Make sure we disable noa to save power. */
			I915_WRITE(RPM_CONFIG1,
			I915_READ(RPM_CONFIG1) & ~GEN10_GT_NOA_ENABLE);
			}

	static void gen7_oa_enable(struct drm_i915_private *dev_priv)		static void gen7_oa_enable(struct drm_i915_private *dev_priv)
	{		{
	/*		/*
	@@ -2937,6 +2948,8 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
	i915_perf_load_test_config_cflgt2(dev_priv);		i915_perf_load_test_config_cflgt2(dev_priv);
	if (IS_CFL_GT3(dev_priv))		if (IS_CFL_GT3(dev_priv))
	i915_perf_load_test_config_cflgt3(dev_priv);		i915_perf_load_test_config_cflgt3(dev_priv);
			} else if (IS_CANNONLAKE(dev_priv)) {
			i915_perf_load_test_config_cnl(dev_priv);
	}		}

	if (dev_priv->perf.oa.test_config.id == 0)		if (dev_priv->perf.oa.test_config.id == 0)
	@@ -3022,6 +3035,12 @@ static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
	(addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg);		(addr >= RPM_CONFIG0.reg && addr <= NOA_CONFIG(8).reg);
	}		}

			static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
			{
			return gen8_is_valid_mux_addr(dev_priv, addr) \|\|
			(addr >= OA_PERFCNT3_LO.reg && addr <= OA_PERFCNT4_HI.reg);
			}

	static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)		static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
	{		{
	return gen7_is_valid_mux_addr(dev_priv, addr) \|\|		return gen7_is_valid_mux_addr(dev_priv, addr) \|\|
	@@ -3475,6 +3494,26 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
	default:		default:
	break;		break;
	}		}
			} else if (IS_GEN10(dev_priv)) {
			dev_priv->perf.oa.ops.is_valid_b_counter_reg =
			gen7_is_valid_b_counter_addr;
			dev_priv->perf.oa.ops.is_valid_mux_reg =
			gen10_is_valid_mux_addr;
			dev_priv->perf.oa.ops.is_valid_flex_reg =
			gen8_is_valid_flex_addr;

			dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set;
			dev_priv->perf.oa.ops.disable_metric_set = gen10_disable_metric_set;

			dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
			dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;

			dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);

			/* Default frequency, although we need to read it from
			* the register as it might vary between parts.
			*/
			dev_priv->perf.oa.timestamp_frequency = 12000000;
	}		}
	}		}

drivers/gpu/drm/i915/i915_reg.h

+5 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1106,6 +1106,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
	#define OA_PERFCNT1_HI _MMIO(0x91BC)		#define OA_PERFCNT1_HI _MMIO(0x91BC)
	#define OA_PERFCNT2_LO _MMIO(0x91C0)		#define OA_PERFCNT2_LO _MMIO(0x91C0)
	#define OA_PERFCNT2_HI _MMIO(0x91C4)		#define OA_PERFCNT2_HI _MMIO(0x91C4)
			#define OA_PERFCNT3_LO _MMIO(0x91C8)
			#define OA_PERFCNT3_HI _MMIO(0x91CC)
			#define OA_PERFCNT4_LO _MMIO(0x91D8)
			#define OA_PERFCNT4_HI _MMIO(0x91DC)

	#define OA_PERFMATRIX_LO _MMIO(0x91C8)		#define OA_PERFMATRIX_LO _MMIO(0x91C8)
	#define OA_PERFMATRIX_HI _MMIO(0x91CC)		#define OA_PERFMATRIX_HI _MMIO(0x91CC)
	@@ -1113,6 +1117,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
	/* RPM unit config (Gen8+) */		/* RPM unit config (Gen8+) */
	#define RPM_CONFIG0 _MMIO(0x0D00)		#define RPM_CONFIG0 _MMIO(0x0D00)
	#define RPM_CONFIG1 _MMIO(0x0D04)		#define RPM_CONFIG1 _MMIO(0x0D04)
			#define GEN10_GT_NOA_ENABLE (1 << 9)

	/* RCP unit config (Gen8+) */		/* RCP unit config (Gen8+) */
	#define RCP_CONFIG _MMIO(0x0D08)		#define RCP_CONFIG _MMIO(0x0D08)

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