Unverified Commit 956284a3 authored by Dilip Kota's avatar Dilip Kota Committed by Mark Brown
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spi: Add bindings for Lightning Mountain SoC



Add support to SPI controller on Intel Atom based Lightning Mountain
SoC which reuses the Lantiq SPI controller IP.

Signed-off-by: default avatarDilip Kota <eswara.kota@linux.intel.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/7d644e5d03ef534f719763e5c823c1673e53d1a5.1594957019.git.eswara.kota@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 040f7f97
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+19 −2
Original line number Diff line number Diff line
Lantiq Synchronous Serial Controller (SSC) SPI master driver

Required properties:
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
  "intel,lgm-spi"
- #address-cells: see spi-bus.txt
- #size-cells: see spi-bus.txt
- reg: address and length of the spi master registers
- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
- interrupts:
  For compatible "intel,lgm-ssc" - the common interrupt number for
  all of tx rx & err interrupts.
       or
  For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
  "spi_err" interrupt.


Optional properties:
@@ -27,3 +33,14 @@ spi: spi@e100800 {
	num-cs = <6>;
	base-cs = <1>;
};

ssc0: spi@e0800000 {
	compatible = "intel,lgm-spi";
	reg = <0xe0800000 0x400>;
	interrupt-parent = <&ioapic1>;
	interrupts = <35 1>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
	clock-names = "freq", "gate";
};