Commit 955c7120 authored by John Clements's avatar John Clements Committed by Alex Deucher
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drm/amdgpu: update UMC 6.1 RAS error counter register access path 



use proper method for SMN register access

Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarJohn Clements <john.clements@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e4b613e0

drivers/gpu/drm/amd/amdgpu/umc_v6_1.c

+5 −5
Original line number Diff line number Diff line
@@ -139,7 +139,7 @@ static void umc_v6_1_query_correctable_error_count(struct amdgpu_device *adev, 


	/* check for SRAM correctable error

	  MCUMC_STATUS is a 64 bit register */

	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);

	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, ErrorCodeExt) == 6 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
@@ -164,7 +164,7 @@ static void umc_v6_1_querry_uncorrectable_error_count(struct amdgpu_device *adev 
	}



	/* check the MCUMC_STATUS */

	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);

	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);

	if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&

	    (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||

	    REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
@@ -211,12 +211,12 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 
	/* skip error address process if -ENOMEM */

	if (!err_data->err_addr) {

		/* clear umc status */

		WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);

		WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

		return;

	}



	err_rec = &err_data->err_addr[err_data->err_addr_cnt];

	mc_umc_status = RREG64_UMC(mc_umc_status_addr + umc_reg_offset);

	mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);



	/* calculate error address if ue/ce error is detected */

	if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
@@ -251,7 +251,7 @@ static void umc_v6_1_query_error_address(struct amdgpu_device *adev, 
	}



	/* clear umc status */

	WREG64_UMC(mc_umc_status_addr + umc_reg_offset, 0x0ULL);

	WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL);

}



static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,

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