ARM: 7649/1: mm: mm->context.id fix for big-endian (9520a5be) · Commits · 戴 / test

Since the new ASID code in ("ARM: mm: remove IPI broadcasting on ASID rollover") was changed to use 64bit operations it has broken the BE operation due to an issue with the MM code accessing sub-fields of mm->context.id. When running in BE mode we see the values in mm->context.id are stored with the highest value first, so the LDR in the arch/arm/mm/proc-macros.S reads the wrong part of this field. To resolve this, change the LDR in the mmid macro to load from +4. Acked-by:

Will Deacon <will.deacon@arm.com> Signed-off-by:

Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:

Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mm/context.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,9 @@
		* The ASID is used to tag entries in the CPU caches and TLBs.
		* The context ID is used by debuggers and trace logic, and
		* should be unique within all running processes.
		*
		* In big endian operation, the two 32 bit words are swapped if accesed by
		* non 64-bit operations.
		*/
		#define ASID_FIRST_VERSION (1ULL << ASID_BITS)
		#define NUM_USER_ASIDS (ASID_FIRST_VERSION - 1)

arch/arm/mm/proc-macros.S

+5 −0

Original line number	Diff line number	Diff line
		@@ -38,9 +38,14 @@

		/*
		* mmid - get context id from mm pointer (mm->context.id)
		* note, this field is 64bit, so in big-endian the two words are swapped too.
		*/
		.macro mmid, rd, rn
		#ifdef __ARMEB__
		ldr \rd, [\rn, #MM_CONTEXT_ID + 4 ]
		#else
		ldr \rd, [\rn, #MM_CONTEXT_ID]
		#endif
		.endm

		/*

Admin message