clk: qcom: Enumerate clocks and reset needed to boot the 8998 modem (95183d38) · Commits · 戴 / test

drivers/clk/qcom/gcc-msm8998.c

+72 −0

Original line number	Diff line number	Diff line
		@@ -1266,6 +1266,72 @@ static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
		},
		};

		static struct clk_branch gcc_mss_cfg_ahb_clk = {
		.halt_reg = 0x8a000,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8a000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_cfg_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_snoc_axi_clk = {
		.halt_reg = 0x8a03c,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8a03c,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_snoc_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
		.halt_reg = 0x8a004,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8a004,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_mnoc_bimc_axi_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_boot_rom_ahb_clk = {
		.halt_reg = 0x38004,
		.halt_check = BRANCH_HALT_VOTED,
		.hwcg_reg = 0x38004,
		.hwcg_bit = 1,
		.clkr = {
		.enable_reg = 0x52004,
		.enable_mask = BIT(10),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_boot_rom_ahb_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_mss_gpll0_div_clk_src = {
		.halt_check = BRANCH_HALT_DELAY,
		.clkr = {
		.enable_reg = 0x5200c,
		.enable_mask = BIT(2),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_mss_gpll0_div_clk_src",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_blsp1_ahb_clk = {
		.halt_reg = 0x17004,
		.halt_check = BRANCH_HALT_VOTED,
		@@ -2832,6 +2898,11 @@ static struct clk_regmap *gcc_msm8998_clocks[] = {
		[GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
		[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
		[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
		[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
		[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
		[GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr,
		[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
		[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
		};

		static struct gdsc *gcc_msm8998_gdscs[] = {
		@@ -2928,6 +2999,7 @@ static const struct qcom_reset_map gcc_msm8998_resets[] = {
		[GCC_GPU_BCR] = { 0x71000 },
		[GCC_SPSS_BCR] = { 0x72000 },
		[GCC_OBT_ODT_BCR] = { 0x73000 },
		[GCC_MSS_RESTART] = { 0x79000 },
		[GCC_VS_BCR] = { 0x7a000 },
		[GCC_MSS_VS_RESET] = { 0x7a100 },
		[GCC_GPU_VS_RESET] = { 0x7a104 },

include/dt-bindings/clock/qcom,gcc-msm8998.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -177,6 +177,11 @@
		#define GCC_UFS_CLKREF_CLK 168
		#define GCC_PCIE_CLKREF_CLK 169
		#define GCC_RX1_USB2_CLKREF_CLK 170
		#define GCC_MSS_CFG_AHB_CLK 171
		#define GCC_BOOT_ROM_AHB_CLK 172
		#define GCC_MSS_GPLL0_DIV_CLK_SRC 173
		#define GCC_MSS_SNOC_AXI_CLK 174
		#define GCC_MSS_MNOC_BIMC_AXI_CLK 175

		#define PCIE_0_GDSC 0
		#define UFS_GDSC 1
		@@ -290,5 +295,6 @@
		#define GCC_MSMPU_BCR 105
		#define GCC_QUSB2PHY_PRIM_BCR 106
		#define GCC_QUSB2PHY_SEC_BCR 107
		#define GCC_MSS_RESTART 108

		#endif

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