Commit 95089f6a authored by Yuantian Tang's avatar Yuantian Tang Committed by Stephen Boyd
Browse files

clk: qoriq: Add ls1028a clock configuration 



Enable clock driver by adding clock configuration for ls1028a chip.

Signed-off-by: default avatarYuantian Tang <andy.tang@nxp.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent cc61ab9b

drivers/clk/clk-qoriq.c

+68 −0
Original line number Diff line number Diff line
@@ -246,6 +246,58 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = { 
	},

};



static const struct clockgen_muxinfo ls1028a_hwa1 = {

	{

		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },

		{},

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },

	},

};



static const struct clockgen_muxinfo ls1028a_hwa2 = {

	{

		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },

		{},

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },

	},

};



static const struct clockgen_muxinfo ls1028a_hwa3 = {

	{

		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },

		{},

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },

	},

};



static const struct clockgen_muxinfo ls1028a_hwa4 = {

	{

		{ CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },

		{ CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },

		{},

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },

		{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },

	},

};



static const struct clockgen_muxinfo ls1043a_hwa1 = {

	{

		{},
@@ -508,6 +560,21 @@ static const struct clockgen_chipinfo chipinfo[] = { 
		},

		.pll_mask = 0x03,

	},

	{

		.compat = "fsl,ls1028a-clockgen",

		.cmux_groups = {

			&clockgen2_cmux_cga12

		},

		.hwaccel = {

			&ls1028a_hwa1, &ls1028a_hwa2,

			&ls1028a_hwa3, &ls1028a_hwa4

		},

		.cmux_to_group = {

			0, 0, 0, 0, -1

		},

		.pll_mask = 0x07,

		.flags = CG_VER3 | CG_LITTLE_ENDIAN,

	},

	{

		.compat = "fsl,ls1043a-clockgen",

		.init_periph = t2080_init_periph,
@@ -1424,6 +1491,7 @@ CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init); 
CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);

CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);

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