Commit 94fa83c4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux 

Pull drm fixes from Dave Airlie:
 "As per your -rc2 announce, this is small and urgent only,

  The radeon one is for a regression in 3.4 so we need this one in your
  tree so we can send the stable one out, code in 3.4 broke some old
  userspaces.  The max props increase fixes spew being seen on a few
  machines.  And a ttm regression to fix some accounting issues that
  affect vmwgfx."

* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
  drm/ttm: Fix buffer object metadata accounting regression v2
  drm: increase DRM_OBJECT_MAX_PROPERTY to 24
  drm/radeon: fix tiling and command stream checking on evergreen v3
parents 266ae4e6 a393c730

drivers/gpu/drm/radeon/evergreen_cs.c

+45 −4
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ struct evergreen_cs_track { 
	u32			cb_color_view[12];

	u32			cb_color_pitch[12];

	u32			cb_color_slice[12];

	u32			cb_color_slice_idx[12];

	u32			cb_color_attrib[12];

	u32			cb_color_cmask_slice[8];/* unused */

	u32			cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track) 
		track->cb_color_info[i] = 0;

		track->cb_color_view[i] = 0xFFFFFFFF;

		track->cb_color_pitch[i] = 0;

		track->cb_color_slice[i] = 0;

		track->cb_color_slice[i] = 0xfffffff;

		track->cb_color_slice_idx[i] = 0;

	}

	track->cb_target_mask = 0xFFFFFFFF;

	track->cb_shader_mask = 0xFFFFFFFF;

	track->cb_dirty = true;



	track->db_depth_slice = 0xffffffff;

	track->db_depth_view = 0xFFFFC000;

	track->db_depth_size = 0xFFFFFFFF;

	track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p, 
{

	struct evergreen_cs_track *track = p->track;

	unsigned palign, halign, tileb, slice_pt;

	unsigned mtile_pr, mtile_ps, mtileb;



	tileb = 64 * surf->bpe * surf->nsamples;

	palign = track->group_size / (8 * surf->bpe * surf->nsamples);

	palign = MAX(8, palign);

	slice_pt = 1;

	if (tileb > surf->tsplit) {

		slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p, 
	/* macro tile width & height */

	palign = (8 * surf->bankw * track->npipes) * surf->mtilea;

	halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;

	surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;

	mtileb = (palign / 8) * (halign / 8) * tileb;;

	mtile_pr = surf->nbx / palign;

	mtile_ps = (mtile_pr * surf->nby) / halign;

	surf->layer_size = mtile_ps * mtileb * slice_pt;

	surf->base_align = (palign / 8) * (halign / 8) * tileb;

	surf->palign = palign;

	surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i 


	offset += surf.layer_size * mslice;

	if (offset > radeon_bo_size(track->cb_color_bo[id])) {

		/* old ddx are broken they allocate bo with w*h*bpp but

		 * program slice with ALIGN(h, 8), catch this and patch

		 * command stream.

		 */

		if (!surf.mode) {

			volatile u32 *ib = p->ib.ptr;

			unsigned long tmp, nby, bsize, size, min = 0;



			/* find the height the ddx wants */

			if (surf.nby > 8) {

				min = surf.nby - 8;

			}

			bsize = radeon_bo_size(track->cb_color_bo[id]);

			tmp = track->cb_color_bo_offset[id] << 8;

			for (nby = surf.nby; nby > min; nby--) {

				size = nby * surf.nbx * surf.bpe * surf.nsamples;

				if ((tmp + size * mslice) <= bsize) {

					break;

				}

			}

			if (nby > min) {

				surf.nby = nby;

				slice = ((nby * surf.nbx) / 64) - 1;

				if (!evergreen_surface_check(p, &surf, "cb")) {

					/* check if this one works */

					tmp += surf.layer_size * mslice;

					if (tmp <= bsize) {

						ib[track->cb_color_slice_idx[id]] = slice;

						goto old_ddx_ok;

					}

				}

			}

		}

		dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "

			 "offset %d, max layer %d, bo size %ld, slice %d)\n",

			 __func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i 
			surf.tsplit, surf.mtilea);

		return -EINVAL;

	}

old_ddx_ok:



	return 0;

}
@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case CB_COLOR7_SLICE:

		tmp = (reg - CB_COLOR0_SLICE) / 0x3c;

		track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);

		track->cb_color_slice_idx[tmp] = idx;

		track->cb_dirty = true;

		break;

	case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) 
	case CB_COLOR11_SLICE:

		tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;

		track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);

		track->cb_color_slice_idx[tmp] = idx;

		track->cb_dirty = true;

		break;

	case CB_COLOR0_ATTRIB:

drivers/gpu/drm/radeon/radeon_drv.c

+2 −1
Original line number Diff line number Diff line
@@ -57,9 +57,10 @@ 
 *   2.13.0 - virtual memory support, streamout

 *   2.14.0 - add evergreen tiling informations

 *   2.15.0 - add max_pipes query

 *   2.16.0 - fix evergreen 2D tiled surface calculation

 */

#define KMS_DRIVER_MAJOR	2

#define KMS_DRIVER_MINOR	15

#define KMS_DRIVER_MINOR	16

#define KMS_DRIVER_PATCHLEVEL	0

int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);

int radeon_driver_unload_kms(struct drm_device *dev);

drivers/gpu/drm/ttm/ttm_bo.c

+3 −10
Original line number Diff line number Diff line
@@ -1204,6 +1204,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev, 
			(*destroy)(bo);

		else

			kfree(bo);

		ttm_mem_global_free(mem_glob, acc_size);

		return -EINVAL;

	}

	bo->destroy = destroy;
@@ -1307,22 +1308,14 @@ int ttm_bo_create(struct ttm_bo_device *bdev, 
			struct ttm_buffer_object **p_bo)

{

	struct ttm_buffer_object *bo;

	struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;

	size_t acc_size;

	int ret;



	acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));

	ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);

	if (unlikely(ret != 0))

		return ret;



	bo = kzalloc(sizeof(*bo), GFP_KERNEL);



	if (unlikely(bo == NULL)) {

		ttm_mem_global_free(mem_glob, acc_size);

	if (unlikely(bo == NULL))

		return -ENOMEM;

	}



	acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));

	ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,

				buffer_start, interruptible,

			  persistent_swap_storage, acc_size, NULL, NULL);

include/drm/drm_crtc.h

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ struct drm_mode_object { 
	struct drm_object_properties *properties;

};



#define DRM_OBJECT_MAX_PROPERTY 16

#define DRM_OBJECT_MAX_PROPERTY 24

struct drm_object_properties {

	int count;

	uint32_t ids[DRM_OBJECT_MAX_PROPERTY];

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