Commit 94c7ca71 authored by Kukjin Kim's avatar Kukjin Kim
Browse files

ARM: EXYNOS: add support for EXYNOS5250 SoC 



This patch add support for EXYNOS5250 SoC has two Cortex-A15 cores.
Since actually, most codes in mach-exynos/ are used commonly for
EXYNOS4 and EXYNOS5 the EXYNOS5/EXYNOS5250 has been implemented
in mach-exynos/.

Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 171c067c

arch/arm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 
machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100

machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210

machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos

machine-$(CONFIG_ARCH_EXYNOS5)		:= exynos

machine-$(CONFIG_ARCH_SA1100)		:= sa1100

machine-$(CONFIG_ARCH_SHARK)		:= shark

machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile

arch/arm/mach-exynos/common.c

+179 −12
Original line number Diff line number Diff line
@@ -49,9 +49,12 @@ 
static const char name_exynos4210[] = "EXYNOS4210";

static const char name_exynos4212[] = "EXYNOS4212";

static const char name_exynos4412[] = "EXYNOS4412";

static const char name_exynos5250[] = "EXYNOS5250";



static void exynos4_map_io(void);

static void exynos5_map_io(void);

static void exynos4_init_clocks(int xtal);

static void exynos5_init_clocks(int xtal);

static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);

static int exynos_init(void);
@@ -80,6 +83,14 @@ static struct cpu_table cpu_ids[] __initdata = { 
		.init_uarts	= exynos_init_uarts,

		.init		= exynos_init,

		.name		= name_exynos4412,

	}, {

		.idcode		= EXYNOS5250_SOC_ID,

		.idmask		= EXYNOS5_SOC_MASK,

		.map_io		= exynos5_map_io,

		.init_clocks	= exynos5_init_clocks,

		.init_uarts	= exynos_init_uarts,

		.init		= exynos_init,

		.name		= name_exynos5250,

	},

};
@@ -88,10 +99,14 @@ static struct cpu_table cpu_ids[] __initdata = { 
static struct map_desc exynos_iodesc[] __initdata = {

	{

		.virtual	= (unsigned long)S5P_VA_CHIPID,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_CHIPID),

		.pfn		= __phys_to_pfn(EXYNOS_PA_CHIPID),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

	},

};



static struct map_desc exynos4_iodesc[] __initdata = {

	{

		.virtual	= (unsigned long)S3C_VA_SYS,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_SYSCON),

		.length		= SZ_64K,
@@ -141,11 +156,7 @@ static struct map_desc exynos_iodesc[] __initdata = { 
		.pfn		= __phys_to_pfn(EXYNOS4_PA_UART),

		.length		= SZ_512K,

		.type		= MT_DEVICE,

	},

};



static struct map_desc exynos4_iodesc[] __initdata = {

	{

	}, {

		.virtual	= (unsigned long)S5P_VA_CMU,

		.pfn		= __phys_to_pfn(EXYNOS4_PA_CMU),

		.length		= SZ_128K,
@@ -206,11 +217,80 @@ static struct map_desc exynos4_iodesc1[] __initdata = { 
	},

};



static struct map_desc exynos5_iodesc[] __initdata = {

	{

		.virtual	= (unsigned long)S3C_VA_SYS,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSCON),

		.length		= SZ_64K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S3C_VA_TIMER,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_TIMER),

		.length		= SZ_16K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S3C_VA_WATCHDOG,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_WATCHDOG),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_SROMC,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_SROMC),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_SYSTIMER,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSTIMER),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_SYSRAM,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_SYSRAM),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_CMU,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_CMU),

		.length		= 144 * SZ_1K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_PMU,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_PMU),

		.length		= SZ_64K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_COMBINER),

		.length		= SZ_4K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S3C_VA_UART,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_UART),

		.length		= SZ_512K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GIC_CPU,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),

		.length		= SZ_64K,

		.type		= MT_DEVICE,

	}, {

		.virtual	= (unsigned long)S5P_VA_GIC_DIST,

		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),

		.length		= SZ_64K,

		.type		= MT_DEVICE,

	},

};



void exynos4_restart(char mode, const char *cmd)

{

	__raw_writel(0x1, S5P_SWRESET);

}



void exynos5_restart(char mode, const char *cmd)

{

	__raw_writel(0x1, EXYNOS_SWRESET);

}



/*

 * exynos_map_io

 *
@@ -261,6 +341,16 @@ static void __init exynos4_map_io(void) 
	s5p_hdmi_setname("exynos4-hdmi");

}



static void __init exynos5_map_io(void)

{

	iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));



	/* The I2C bus controllers are directly compatible with s3c2440 */

	s3c_i2c0_setname("s3c2440-i2c");

	s3c_i2c1_setname("s3c2440-i2c");

	s3c_i2c2_setname("s3c2440-i2c");

}



static void __init exynos4_init_clocks(int xtal)

{

	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
@@ -277,6 +367,17 @@ static void __init exynos4_init_clocks(int xtal) 
	exynos4_setup_clocks();

}



static void __init exynos5_init_clocks(int xtal)

{

	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);



	s3c24xx_register_baseclocks(xtal);

	s5p_register_clocks(xtal);



	exynos5_register_clocks();

	exynos5_setup_clocks();

}



#define COMBINER_ENABLE_SET	0x0

#define COMBINER_ENABLE_CLEAR	0x4

#define COMBINER_INT_STATUS	0xC
@@ -420,24 +521,59 @@ void __init exynos4_init_irq(void) 
	s5p_init_irq(NULL, 0);

}



void __init exynos5_init_irq(void)

{

	int irq;



	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);



	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {

		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

				COMBINER_IRQ(irq, 0));

		combiner_cascade_irq(irq, IRQ_SPI(irq));

	}



	/*

	 * The parameters of s5p_init_irq() are for VIC init.

	 * Theses parameters should be NULL and 0 because EXYNOS4

	 * uses GIC instead of VIC.

	 */

	s5p_init_irq(NULL, 0);

}



struct bus_type exynos4_subsys = {

	.name		= "exynos4-core",

	.dev_name	= "exynos4-core",

};



struct bus_type exynos5_subsys = {

	.name		= "exynos5-core",

	.dev_name	= "exynos5-core",

};



static struct device exynos4_dev = {

	.bus	= &exynos4_subsys,

};



static int __init exynos4_core_init(void)

static struct device exynos5_dev = {

	.bus	= &exynos5_subsys,

};



static int __init exynos_core_init(void)

{

	if (soc_is_exynos5250())

		return subsys_system_register(&exynos5_subsys, NULL);

	else

		return subsys_system_register(&exynos4_subsys, NULL);

}

core_initcall(exynos4_core_init);

core_initcall(exynos_core_init);



#ifdef CONFIG_CACHE_L2X0

static int __init exynos4_l2x0_cache_init(void)

{

	if (soc_is_exynos5250())

		return 0;



	/* TAG, Data Latency Control: 2cycle */

	__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@@ -457,13 +593,41 @@ static int __init exynos4_l2x0_cache_init(void) 


	return 0;

}



early_initcall(exynos4_l2x0_cache_init);

#endif



static int __init exynos5_l2_cache_init(void)

{

	unsigned int val;



	if (!soc_is_exynos5250())

		return 0;



	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"

		     "bic %0, %0, #(1 << 2)\n"	/* cache disable */

		     "mcr p15, 0, %0, c1, c0, 0\n"

		     "mrc p15, 1, %0, c9, c0, 2\n"

		     : "=r"(val));



	val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);



	asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));

	asm volatile("mrc p15, 0, %0, c1, c0, 0\n"

		     "orr %0, %0, #(1 << 2)\n"	/* cache enable */

		     "mcr p15, 0, %0, c1, c0, 0\n"

		     : : "r"(val));



	return 0;

}

early_initcall(exynos5_l2_cache_init);



static int __init exynos_init(void)

{

	printk(KERN_INFO "EXYNOS: Initializing architecture\n");



	if (soc_is_exynos5250())

		return device_register(&exynos5_dev);

	else

		return device_register(&exynos4_dev);

}
@@ -673,6 +837,9 @@ static int __init exynos4_init_irq_eint(void) 
{

	int irq;



	if (soc_is_exynos5250())

		return 0;



	for (irq = 0 ; irq <= 31 ; irq++) {

		irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,

					 handle_level_irq);

arch/arm/mach-exynos/common.h

+11 −0
Original line number Diff line number Diff line
@@ -16,7 +16,9 @@ extern struct sys_timer exynos4_timer; 


void exynos_init_io(struct map_desc *mach_desc, int size);

void exynos4_init_irq(void);

void exynos5_init_irq(void);

void exynos4_restart(char mode, const char *cmd);

void exynos5_restart(char mode, const char *cmd);



#ifdef CONFIG_ARCH_EXYNOS4

void exynos4_register_clocks(void);
@@ -27,6 +29,15 @@ void exynos4_setup_clocks(void); 
#define exynos4_setup_clocks()

#endif



#ifdef CONFIG_ARCH_EXYNOS5

void exynos5_register_clocks(void);

void exynos5_setup_clocks(void);



#else

#define exynos5_register_clocks()

#define exynos5_setup_clocks()

#endif



#ifdef CONFIG_CPU_EXYNOS4210

void exynos4210_register_clocks(void);

arch/arm/mach-exynos/include/mach/map.h

+19 −2
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#define EXYNOS4_PA_SYSRAM0		0x02025000

#define EXYNOS4_PA_SYSRAM1		0x02020000

#define EXYNOS5_PA_SYSRAM		0x02020000



#define EXYNOS4_PA_FIMC0		0x11800000

#define EXYNOS4_PA_FIMC1		0x11810000
@@ -44,14 +45,23 @@ 
#define EXYNOS4_PA_ONENAND		0x0C000000

#define EXYNOS4_PA_ONENAND_DMA		0x0C600000



#define EXYNOS4_PA_CHIPID		0x10000000

#define EXYNOS_PA_CHIPID		0x10000000



#define EXYNOS4_PA_SYSCON		0x10010000

#define EXYNOS5_PA_SYSCON		0x10050100



#define EXYNOS4_PA_PMU			0x10020000

#define EXYNOS5_PA_PMU			0x10040000



#define EXYNOS4_PA_CMU			0x10030000

#define EXYNOS5_PA_CMU			0x10010000



#define EXYNOS4_PA_SYSTIMER		0x10050000

#define EXYNOS5_PA_SYSTIMER		0x101C0000



#define EXYNOS4_PA_WATCHDOG		0x10060000

#define EXYNOS5_PA_WATCHDOG		0x101D0000



#define EXYNOS4_PA_RTC			0x10070000



#define EXYNOS4_PA_KEYPAD		0x100A0000
@@ -59,9 +69,12 @@ 
#define EXYNOS4_PA_DMC0			0x10400000



#define EXYNOS4_PA_COMBINER		0x10440000

#define EXYNOS5_PA_COMBINER		0x10440000



#define EXYNOS4_PA_GIC_CPU		0x10480000

#define EXYNOS4_PA_GIC_DIST		0x10490000

#define EXYNOS5_PA_GIC_CPU		0x10480000

#define EXYNOS5_PA_GIC_DIST		0x10490000



#define EXYNOS4_PA_COREPERI		0x10500000

#define EXYNOS4_PA_TWD			0x10500600
@@ -92,7 +105,6 @@ 
#define EXYNOS4_PA_SPI1			0x13930000

#define EXYNOS4_PA_SPI2			0x13940000





#define EXYNOS4_PA_GPIO1		0x11400000

#define EXYNOS4_PA_GPIO2		0x11000000

#define EXYNOS4_PA_GPIO3		0x03860000
@@ -110,6 +122,7 @@ 
#define EXYNOS4_PA_SATAPHY_CTRL		0x126B0000



#define EXYNOS4_PA_SROMC		0x12570000

#define EXYNOS5_PA_SROMC		0x12250000



#define EXYNOS4_PA_EHCI			0x12580000

#define EXYNOS4_PA_OHCI			0x12590000
@@ -117,6 +130,7 @@ 
#define EXYNOS4_PA_MFC			0x13400000



#define EXYNOS4_PA_UART			0x13800000

#define EXYNOS5_PA_UART			0x12C00000



#define EXYNOS4_PA_VP			0x12C00000

#define EXYNOS4_PA_MIXER		0x12C10000
@@ -125,6 +139,7 @@ 
#define EXYNOS4_PA_IIC_HDMIPHY		0x138E0000



#define EXYNOS4_PA_IIC(x)		(0x13860000 + ((x) * 0x10000))

#define EXYNOS5_PA_IIC(x)		(0x12C60000 + ((x) * 0x10000))



#define EXYNOS4_PA_ADC			0x13910000

#define EXYNOS4_PA_ADC1			0x13911000
@@ -134,8 +149,10 @@ 
#define EXYNOS4_PA_SPDIF		0x139B0000



#define EXYNOS4_PA_TIMER		0x139D0000

#define EXYNOS5_PA_TIMER		0x12DD0000



#define EXYNOS4_PA_SDRAM		0x40000000

#define EXYNOS5_PA_SDRAM		0x40000000



/* Compatibiltiy Defines */

arch/arm/mach-exynos/include/mach/regs-pmu.h

+1 −0
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)



#define S5P_SWRESET				S5P_PMUREG(0x0400)

#define EXYNOS_SWRESET				S5P_PMUREG(0x0400)



#define S5P_WAKEUP_STAT				S5P_PMUREG(0x0600)

#define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)

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