Commit 94bfb75a authored by Markos Chandras's avatar Markos Chandras
Browse files

MIPS: asm: Rename GCC_OFF12_ASM to GCC_OFF_SMALL_ASM 



The GCC_OFF12_ASM macro is used for 12-bit immediate constrains
but we will also use it for 9-bit constrains on MIPS R6 so we
rename it to something more appropriate.

Cc: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent a7e07b1a

arch/mips/include/asm/atomic.h

+15 −15
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \ 
		"	sc	%0, %1					\n"   \

		"	beqzl	%0, 1b					\n"   \

		"	.set	mips0					\n"   \

		: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter)	      \

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter)	      \

		: "Ir" (i));						      \

	} else if (kernel_uses_llsc) {					      \

		int temp;						      \
@@ -66,7 +66,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) \ 
			"	" #asm_op " %0, %2			\n"   \

			"	sc	%0, %1				\n"   \

			"	.set	mips0				\n"   \

			: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter)      \

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter)      \

			: "Ir" (i));					      \

		} while (unlikely(!temp));				      \

	} else {							      \
@@ -97,7 +97,7 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \ 
		"	" #asm_op " %0, %1, %3				\n"   \

		"	.set	mips0					\n"   \

		: "=&r" (result), "=&r" (temp),				      \

		  "+" GCC_OFF12_ASM() (v->counter)			      \

		  "+" GCC_OFF_SMALL_ASM() (v->counter)			      \

		: "Ir" (i));						      \

	} else if (kernel_uses_llsc) {					      \

		int temp;						      \
@@ -110,7 +110,7 @@ static __inline__ int atomic_##op##_return(int i, atomic_t * v) \ 
			"	sc	%0, %2				\n"   \

			"	.set	mips0				\n"   \

			: "=&r" (result), "=&r" (temp),			      \

			  "+" GCC_OFF12_ASM() (v->counter)		      \

			  "+" GCC_OFF_SMALL_ASM() (v->counter)		      \

			: "Ir" (i));					      \

		} while (unlikely(!result));				      \

									      \
@@ -171,8 +171,8 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 
		"1:							\n"

		"	.set	mips0					\n"

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF12_ASM() (v->counter)

		: "Ir" (i), GCC_OFF12_ASM() (v->counter)

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)

		: "memory");

	} else if (kernel_uses_llsc) {

		int temp;
@@ -190,7 +190,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) 
		"1:							\n"

		"	.set	mips0					\n"

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF12_ASM() (v->counter)

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "Ir" (i));

	} else {

		unsigned long flags;
@@ -333,7 +333,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \ 
		"	scd	%0, %1					\n"   \

		"	beqzl	%0, 1b					\n"   \

		"	.set	mips0					\n"   \

		: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter)	      \

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter)	      \

		: "Ir" (i));						      \

	} else if (kernel_uses_llsc) {					      \

		long temp;						      \
@@ -345,7 +345,7 @@ static __inline__ void atomic64_##op(long i, atomic64_t * v) \ 
			"	" #asm_op " %0, %2			\n"   \

			"	scd	%0, %1				\n"   \

			"	.set	mips0				\n"   \

			: "=&r" (temp), "+" GCC_OFF12_ASM() (v->counter)      \

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter)      \

			: "Ir" (i));					      \

		} while (unlikely(!temp));				      \

	} else {							      \
@@ -376,7 +376,7 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \ 
		"	" #asm_op " %0, %1, %3				\n"   \

		"	.set	mips0					\n"   \

		: "=&r" (result), "=&r" (temp),				      \

		  "+" GCC_OFF12_ASM() (v->counter)			      \

		  "+" GCC_OFF_SMALL_ASM() (v->counter)			      \

		: "Ir" (i));						      \

	} else if (kernel_uses_llsc) {					      \

		long temp;						      \
@@ -389,8 +389,8 @@ static __inline__ long atomic64_##op##_return(long i, atomic64_t * v) \ 
			"	scd	%0, %2				\n"   \

			"	.set	mips0				\n"   \

			: "=&r" (result), "=&r" (temp),			      \

			  "=" GCC_OFF12_ASM() (v->counter)		      \

			: "Ir" (i), GCC_OFF12_ASM() (v->counter)	      \

			  "=" GCC_OFF_SMALL_ASM() (v->counter)		      \

			: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)	      \

			: "memory");					      \

		} while (unlikely(!result));				      \

									      \
@@ -452,8 +452,8 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 
		"1:							\n"

		"	.set	mips0					\n"

		: "=&r" (result), "=&r" (temp),

		  "=" GCC_OFF12_ASM() (v->counter)

		: "Ir" (i), GCC_OFF12_ASM() (v->counter)

		  "=" GCC_OFF_SMALL_ASM() (v->counter)

		: "Ir" (i), GCC_OFF_SMALL_ASM() (v->counter)

		: "memory");

	} else if (kernel_uses_llsc) {

		long temp;
@@ -471,7 +471,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) 
		"1:							\n"

		"	.set	mips0					\n"

		: "=&r" (result), "=&r" (temp),

		  "+" GCC_OFF12_ASM() (v->counter)

		  "+" GCC_OFF_SMALL_ASM() (v->counter)

		: "Ir" (i));

	} else {

		unsigned long flags;

arch/mips/include/asm/bitops.h

+17 −17
Original line number Diff line number Diff line
@@ -79,8 +79,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
		"	" __SC	"%0, %1					\n"

		"	beqzl	%0, 1b					\n"

		"	.set	mips0					\n"

		: "=&r" (temp), "=" GCC_OFF12_ASM() (*m)

		: "ir" (1UL << bit), GCC_OFF12_ASM() (*m));

		: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*m)

		: "ir" (1UL << bit), GCC_OFF_SMALL_ASM() (*m));

#ifdef CONFIG_CPU_MIPSR2

	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {

		do {
@@ -88,7 +88,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
			"	" __LL "%0, %1		# set_bit	\n"

			"	" __INS "%0, %3, %2, 1			\n"

			"	" __SC "%0, %1				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

			: "ir" (bit), "r" (~0));

		} while (unlikely(!temp));

#endif /* CONFIG_CPU_MIPSR2 */
@@ -100,7 +100,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) 
			"	or	%0, %2				\n"

			"	" __SC	"%0, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

			: "ir" (1UL << bit));

		} while (unlikely(!temp));

	} else
@@ -131,7 +131,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
		"	" __SC "%0, %1					\n"

		"	beqzl	%0, 1b					\n"

		"	.set	mips0					\n"

		: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

		: "ir" (~(1UL << bit)));

#ifdef CONFIG_CPU_MIPSR2

	} else if (kernel_uses_llsc && __builtin_constant_p(bit)) {
@@ -140,7 +140,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
			"	" __LL "%0, %1		# clear_bit	\n"

			"	" __INS "%0, $0, %2, 1			\n"

			"	" __SC "%0, %1				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

			: "ir" (bit));

		} while (unlikely(!temp));

#endif /* CONFIG_CPU_MIPSR2 */
@@ -152,7 +152,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) 
			"	and	%0, %2				\n"

			"	" __SC "%0, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

			: "ir" (~(1UL << bit)));

		} while (unlikely(!temp));

	} else
@@ -197,7 +197,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
		"	" __SC	"%0, %1				\n"

		"	beqzl	%0, 1b				\n"

		"	.set	mips0				\n"

		: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

		: "ir" (1UL << bit));

	} else if (kernel_uses_llsc) {

		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -210,7 +210,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) 
			"	xor	%0, %2				\n"

			"	" __SC	"%0, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m)

			: "ir" (1UL << bit));

		} while (unlikely(!temp));

	} else
@@ -245,7 +245,7 @@ static inline int test_and_set_bit(unsigned long nr, 
		"	beqzl	%2, 1b					\n"

		"	and	%2, %0, %3				\n"

		"	.set	mips0					\n"

		: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

		: "r" (1UL << bit)

		: "memory");

	} else if (kernel_uses_llsc) {
@@ -259,7 +259,7 @@ static inline int test_and_set_bit(unsigned long nr, 
			"	or	%2, %0, %3			\n"

			"	" __SC	"%2, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

			: "r" (1UL << bit)

			: "memory");

		} while (unlikely(!res));
@@ -313,7 +313,7 @@ static inline int test_and_set_bit_lock(unsigned long nr, 
			"	or	%2, %0, %3			\n"

			"	" __SC	"%2, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

			: "r" (1UL << bit)

			: "memory");

		} while (unlikely(!res));
@@ -355,7 +355,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
		"	beqzl	%2, 1b					\n"

		"	and	%2, %0, %3				\n"

		"	.set	mips0					\n"

		: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

		: "r" (1UL << bit)

		: "memory");

#ifdef CONFIG_CPU_MIPSR2
@@ -369,7 +369,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
			"	" __EXT "%2, %0, %3, 1			\n"

			"	" __INS "%0, $0, %3, 1			\n"

			"	" __SC	"%0, %1				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

			: "ir" (bit)

			: "memory");

		} while (unlikely(!temp));
@@ -386,7 +386,7 @@ static inline int test_and_clear_bit(unsigned long nr, 
			"	xor	%2, %3				\n"

			"	" __SC	"%2, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

			: "r" (1UL << bit)

			: "memory");

		} while (unlikely(!res));
@@ -428,7 +428,7 @@ static inline int test_and_change_bit(unsigned long nr, 
		"	beqzl	%2, 1b					\n"

		"	and	%2, %0, %3				\n"

		"	.set	mips0					\n"

		: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

		: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

		: "r" (1UL << bit)

		: "memory");

	} else if (kernel_uses_llsc) {
@@ -442,7 +442,7 @@ static inline int test_and_change_bit(unsigned long nr, 
			"	xor	%2, %0, %3			\n"

			"	" __SC	"\t%2, %1			\n"

			"	.set	mips0				\n"

			: "=&r" (temp), "+" GCC_OFF12_ASM() (*m), "=&r" (res)

			: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=&r" (res)

			: "r" (1UL << bit)

			: "memory");

		} while (unlikely(!res));

arch/mips/include/asm/cmpxchg.h

+12 −12
Original line number Diff line number Diff line
@@ -31,8 +31,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 
		"	sc	%2, %1					\n"

		"	beqzl	%2, 1b					\n"

		"	.set	mips0					\n"

		: "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)

		: GCC_OFF12_ASM() (*m), "Jr" (val)

		: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)

		: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)

		: "memory");

	} else if (kernel_uses_llsc) {

		unsigned long dummy;
@@ -46,9 +46,9 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) 
			"	.set	arch=r4000			\n"

			"	sc	%2, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (retval), "=" GCC_OFF12_ASM() (*m),

			: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),

			  "=&r" (dummy)

			: GCC_OFF12_ASM() (*m), "Jr" (val)

			: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)

			: "memory");

		} while (unlikely(!dummy));

	} else {
@@ -82,8 +82,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) 
		"	scd	%2, %1					\n"

		"	beqzl	%2, 1b					\n"

		"	.set	mips0					\n"

		: "=&r" (retval), "=" GCC_OFF12_ASM() (*m), "=&r" (dummy)

		: GCC_OFF12_ASM() (*m), "Jr" (val)

		: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m), "=&r" (dummy)

		: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)

		: "memory");

	} else if (kernel_uses_llsc) {

		unsigned long dummy;
@@ -95,9 +95,9 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) 
			"	move	%2, %z4				\n"

			"	scd	%2, %1				\n"

			"	.set	mips0				\n"

			: "=&r" (retval), "=" GCC_OFF12_ASM() (*m),

			: "=&r" (retval), "=" GCC_OFF_SMALL_ASM() (*m),

			  "=&r" (dummy)

			: GCC_OFF12_ASM() (*m), "Jr" (val)

			: GCC_OFF_SMALL_ASM() (*m), "Jr" (val)

			: "memory");

		} while (unlikely(!dummy));

	} else {
@@ -158,8 +158,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz 
		"	beqzl	$1, 1b				\n"	\

		"2:						\n"	\

		"	.set	pop				\n"	\

		: "=&r" (__ret), "=" GCC_OFF12_ASM() (*m)		\

		: GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new)		\

		: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)		\

		: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new)		\

		: "memory");						\

	} else if (kernel_uses_llsc) {					\

		__asm__ __volatile__(					\
@@ -175,8 +175,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz 
		"	beqz	$1, 1b				\n"	\

		"	.set	pop				\n"	\

		"2:						\n"	\

		: "=&r" (__ret), "=" GCC_OFF12_ASM() (*m)		\

		: GCC_OFF12_ASM() (*m), "Jr" (old), "Jr" (new)		\

		: "=&r" (__ret), "=" GCC_OFF_SMALL_ASM() (*m)		\

		: GCC_OFF_SMALL_ASM() (*m), "Jr" (old), "Jr" (new)		\

		: "memory");						\

	} else {							\

		unsigned long __flags;					\

arch/mips/include/asm/compiler.h

+2 −2
Original line number Diff line number Diff line
@@ -17,9 +17,9 @@ 
#endif



#ifndef CONFIG_CPU_MICROMIPS

#define GCC_OFF12_ASM() "R"

#define GCC_OFF_SMALL_ASM() "R"

#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9)

#define GCC_OFF12_ASM() "ZC"

#define GCC_OFF_SMALL_ASM() "ZC"

#else

#error "microMIPS compilation unsupported with GCC older than 4.9"

#endif

arch/mips/include/asm/edac.h

+2 −2
Original line number Diff line number Diff line
@@ -26,8 +26,8 @@ static inline void atomic_scrub(void *va, u32 size) 
		"	sc	%0, %1					\n"

		"	beqz	%0, 1b					\n"

		"	.set	mips0					\n"

		: "=&r" (temp), "=" GCC_OFF12_ASM() (*virt_addr)

		: GCC_OFF12_ASM() (*virt_addr));

		: "=&r" (temp), "=" GCC_OFF_SMALL_ASM() (*virt_addr)

		: GCC_OFF_SMALL_ASM() (*virt_addr));



		virt_addr++;

	}

CRA Git | Maintained and supported by SUSTech CRA and CCSE