Commit 94af7a3c authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

clk: samsung: exynos4: Add SSS gate clock 



Add a gate clock for controlling all clocks of Security Sub System
(SSS).

Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 8005c49d

drivers/clk/samsung/clk-exynos4.c

+1 −0
Original line number Diff line number Diff line
@@ -1024,6 +1024,7 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { 
			0, 0),

	GATE(CLK_AC97, "ac97", "aclk100", GATE_IP_PERIL, 27,

			0, 0),

	GATE(CLK_SSS, "sss", "aclk133", GATE_IP_DMC, 4, 0, 0),

	GATE(CLK_PPMUDMC0, "ppmudmc0", "aclk133", GATE_IP_DMC, 8, 0, 0),

	GATE(CLK_PPMUDMC1, "ppmudmc1", "aclk133", GATE_IP_DMC, 9, 0, 0),

	GATE(CLK_PPMUCPU, "ppmucpu", "aclk133", GATE_IP_DMC, 10, 0, 0),

include/dt-bindings/clock/exynos4.h

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ 
#define CLK_SCLK_FIMG2D		177



/* gate clocks */

#define CLK_SSS			255

#define CLK_FIMC0		256

#define CLK_FIMC1		257

#define CLK_FIMC2		258

CRA Git | Maintained and supported by SUSTech CRA and CCSE