Commit 94a5181f authored by Sasha Neftin's avatar Sasha Neftin Committed by Tony Nguyen
Browse files

igc: Fix registers definition 



IGC_ICTXPTC and IGC_ICTXATC are already defined elsewhere, remove this
double definition. Also, remove unneeded registers as they are not
applicable to i225 devices.

Signed-off-by: default avatarSasha Neftin <sasha.neftin@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent ed6ab19a

drivers/net/ethernet/intel/igc/igc_hw.h

+0 −4
Original line number Diff line number Diff line
@@ -276,12 +276,8 @@ struct igc_hw_stats { 
	u64 tsctc;

	u64 tsctfc;

	u64 iac;

	u64 icrxptc;

	u64 icrxatc;

	u64 ictxptc;

	u64 ictxatc;

	u64 icrxdmtc;

	u64 icrxoc;

	u64 cbtmpc;

	u64 htdpmc;

	u64 cbrdpc;

drivers/net/ethernet/intel/igc/igc_mac.c

+0 −4
Original line number Diff line number Diff line
@@ -295,13 +295,9 @@ void igc_clear_hw_cntrs_base(struct igc_hw *hw) 
	rd32(IGC_MGTPTC);



	rd32(IGC_IAC);

	rd32(IGC_ICRXOC);



	rd32(IGC_ICRXPTC);

	rd32(IGC_ICRXATC);

	rd32(IGC_ICTXPTC);

	rd32(IGC_ICTXATC);

	rd32(IGC_ICRXDMTC);



	rd32(IGC_RPTHC);

	rd32(IGC_TLPIC);

drivers/net/ethernet/intel/igc/igc_main.c

+0 −4
Original line number Diff line number Diff line
@@ -3730,12 +3730,8 @@ void igc_update_stats(struct igc_adapter *adapter) 
	adapter->stats.tsctc += rd32(IGC_TSCTC);



	adapter->stats.iac += rd32(IGC_IAC);

	adapter->stats.icrxoc += rd32(IGC_ICRXOC);

	adapter->stats.icrxptc += rd32(IGC_ICRXPTC);

	adapter->stats.icrxatc += rd32(IGC_ICRXATC);

	adapter->stats.ictxptc += rd32(IGC_ICTXPTC);

	adapter->stats.ictxatc += rd32(IGC_ICTXATC);

	adapter->stats.icrxdmtc += rd32(IGC_ICRXDMTC);



	/* Fill out the OS statistics structure */

	net_stats->multicast = adapter->stats.mprc;

drivers/net/ethernet/intel/igc/igc_regs.h

+0 −8
Original line number Diff line number Diff line
@@ -58,14 +58,6 @@ 
#define IGC_IVAR_MISC		0x01740  /* IVAR for "other" causes - RW */

#define IGC_GPIE		0x01514  /* General Purpose Intr Enable - RW */



/* Interrupt Cause */

#define IGC_ICRXPTC		0x04104  /* Rx Packet Timer Expire Count */

#define IGC_ICRXATC		0x04108  /* Rx Absolute Timer Expire Count */

#define IGC_ICTXPTC		0x0410C  /* Tx Packet Timer Expire Count */

#define IGC_ICTXATC		0x04110  /* Tx Absolute Timer Expire Count */

#define IGC_ICRXDMTC		0x04120  /* Rx Descriptor Min Threshold Count */

#define IGC_ICRXOC		0x04124  /* Receiver Overrun Count */



/* MSI-X Table Register Descriptions */

#define IGC_PBACL		0x05B68  /* MSIx PBA Clear - R/W 1 to clear */

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