Commit 94a4c329 authored by Atsushi Nemoto's avatar Atsushi Nemoto Committed by Ralf Baechle
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[MIPS] TXx9: Add 64-bit support 



SYS_SUPPORTS_64BIT_KERNEL is enabled for RBTX4927/RBTX4938, but
actually it was broken for long time (or from the beginning).  Now it
should work.

Signed-off-by: default avatarAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 255033a9

arch/mips/txx9/generic/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ 


obj-y	+= setup.o

obj-$(CONFIG_PCI)	+= pci.o

obj-$(CONFIG_SOC_TX4927)	+= mem_tx4927.o irq_tx4927.o

obj-$(CONFIG_SOC_TX4938)	+= mem_tx4927.o irq_tx4938.o

obj-$(CONFIG_SOC_TX4927)	+= mem_tx4927.o setup_tx4927.o irq_tx4927.o

obj-$(CONFIG_SOC_TX4938)	+= mem_tx4927.o setup_tx4938.o irq_tx4938.o

obj-$(CONFIG_TOSHIBA_FPCIB0)	+= smsc_fdc37m81x.o

obj-$(CONFIG_KGDB)	+= dbgio.o

arch/mips/txx9/generic/irq_tx4927.c

+1 −1
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ 
void __init tx4927_irq_init(void)

{

	mips_cpu_irq_init();

	txx9_irq_init(TX4927_IRC_REG);

	txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);

	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,

				handle_simple_irq);

}

arch/mips/txx9/generic/irq_tx4938.c

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
void __init tx4938_irq_init(void)

{

	mips_cpu_irq_init();

	txx9_irq_init(TX4938_IRC_REG);

	txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);

	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,

				handle_simple_irq);

}

arch/mips/txx9/generic/setup.c

+14 −2
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ struct resource txx9_ce_res[8]; 
static char txx9_ce_res_name[8][4];	/* "CEn" */



/* pcode, internal register */

unsigned int txx9_pcode;

char txx9_pcode_str[8];

static struct resource txx9_reg_res = {

	.name = txx9_pcode_str,
@@ -59,15 +60,16 @@ unsigned int txx9_master_clock; 
unsigned int txx9_cpu_clock;

unsigned int txx9_gbus_clock;



int txx9_ccfg_toeon __initdata = 1;



/* Minimum CLK support */



struct clk *clk_get(struct device *dev, const char *id)

{

	if (!strcmp(id, "spi-baseclk"))

		return (struct clk *)(txx9_gbus_clock / 2 / 4);

		return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4);

	if (!strcmp(id, "imbus_clk"))

		return (struct clk *)(txx9_gbus_clock / 2);

		return (struct clk *)((unsigned long)txx9_gbus_clock / 2);

	return ERR_PTR(-ENOENT);

}

EXPORT_SYMBOL(clk_get);
@@ -123,6 +125,12 @@ void __init prom_init_cmdline(void) 
	int argc = (int)fw_arg0;

	char **argv = (char **)fw_arg1;

	int i;			/* Always ignore the "-c" at argv[0] */

#ifdef CONFIG_64BIT

	char *fixed_argv[32];

	for (i = 0; i < argc; i++)

		fixed_argv[i] = (char *)(long)(*((__s32 *)argv + i));

	argv = fixed_argv;

#endif



	/* ignore all built-in args if any f/w args given */

	if (argc > 1)
@@ -180,6 +188,10 @@ char * __init prom_getcmdline(void) 
/* wrappers */

void __init plat_mem_setup(void)

{

	ioport_resource.start = 0;

	ioport_resource.end = ~0UL;	/* no limit */

	iomem_resource.start = 0;

	iomem_resource.end = ~0UL;	/* no limit */

	txx9_board_vec->mem_setup();

}

arch/mips/txx9/generic/setup_tx4927.c

0 → 100644
+194 −0
Original line number Diff line number Diff line 
/*

 * TX4927 setup routines

 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,

 *	    and RBTX49xx patch from CELF patch archive.

 *

 * 2003-2005 (c) MontaVista Software, Inc.

 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007

 *

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 */

#include <linux/init.h>

#include <linux/ioport.h>

#include <linux/delay.h>

#include <linux/serial_core.h>

#include <linux/param.h>

#include <asm/txx9irq.h>

#include <asm/txx9tmr.h>

#include <asm/txx9pio.h>

#include <asm/txx9/generic.h>

#include <asm/txx9/tx4927.h>



void __init tx4927_wdr_init(void)

{

	/* clear WatchDogReset (W1C) */

	tx4927_ccfg_set(TX4927_CCFG_WDRST);

	/* do reset on watchdog */

	tx4927_ccfg_set(TX4927_CCFG_WR);

}



static struct resource tx4927_sdram_resource[4];



void __init tx4927_setup(void)

{

	int i;

	__u32 divmode;

	int cpuclk = 0;

	u64 ccfg;



	txx9_reg_res_init(TX4927_REV_PCODE(), TX4927_REG_BASE,

			  TX4927_REG_SIZE);



	/* SDRAMC,EBUSC are configured by PROM */

	for (i = 0; i < 8; i++) {

		if (!(TX4927_EBUSC_CR(i) & 0x8))

			continue;	/* disabled */

		txx9_ce_res[i].start = (unsigned long)TX4927_EBUSC_BA(i);

		txx9_ce_res[i].end =

			txx9_ce_res[i].start + TX4927_EBUSC_SIZE(i) - 1;

		request_resource(&iomem_resource, &txx9_ce_res[i]);

	}



	/* clocks */

	ccfg = ____raw_readq(&tx4927_ccfgptr->ccfg);

	if (txx9_master_clock) {

		/* calculate gbus_clock and cpu_clock from master_clock */

		divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;

		switch (divmode) {

		case TX4927_CCFG_DIVMODE_8:

		case TX4927_CCFG_DIVMODE_10:

		case TX4927_CCFG_DIVMODE_12:

		case TX4927_CCFG_DIVMODE_16:

			txx9_gbus_clock = txx9_master_clock * 4; break;

		default:

			txx9_gbus_clock = txx9_master_clock;

		}

		switch (divmode) {

		case TX4927_CCFG_DIVMODE_2:

		case TX4927_CCFG_DIVMODE_8:

			cpuclk = txx9_gbus_clock * 2; break;

		case TX4927_CCFG_DIVMODE_2_5:

		case TX4927_CCFG_DIVMODE_10:

			cpuclk = txx9_gbus_clock * 5 / 2; break;

		case TX4927_CCFG_DIVMODE_3:

		case TX4927_CCFG_DIVMODE_12:

			cpuclk = txx9_gbus_clock * 3; break;

		case TX4927_CCFG_DIVMODE_4:

		case TX4927_CCFG_DIVMODE_16:

			cpuclk = txx9_gbus_clock * 4; break;

		}

		txx9_cpu_clock = cpuclk;

	} else {

		if (txx9_cpu_clock == 0)

			txx9_cpu_clock = 200000000;	/* 200MHz */

		/* calculate gbus_clock and master_clock from cpu_clock */

		cpuclk = txx9_cpu_clock;

		divmode = (__u32)ccfg & TX4927_CCFG_DIVMODE_MASK;

		switch (divmode) {

		case TX4927_CCFG_DIVMODE_2:

		case TX4927_CCFG_DIVMODE_8:

			txx9_gbus_clock = cpuclk / 2; break;

		case TX4927_CCFG_DIVMODE_2_5:

		case TX4927_CCFG_DIVMODE_10:

			txx9_gbus_clock = cpuclk * 2 / 5; break;

		case TX4927_CCFG_DIVMODE_3:

		case TX4927_CCFG_DIVMODE_12:

			txx9_gbus_clock = cpuclk / 3; break;

		case TX4927_CCFG_DIVMODE_4:

		case TX4927_CCFG_DIVMODE_16:

			txx9_gbus_clock = cpuclk / 4; break;

		}

		switch (divmode) {

		case TX4927_CCFG_DIVMODE_8:

		case TX4927_CCFG_DIVMODE_10:

		case TX4927_CCFG_DIVMODE_12:

		case TX4927_CCFG_DIVMODE_16:

			txx9_master_clock = txx9_gbus_clock / 4; break;

		default:

			txx9_master_clock = txx9_gbus_clock;

		}

	}

	/* change default value to udelay/mdelay take reasonable time */

	loops_per_jiffy = txx9_cpu_clock / HZ / 2;



	/* CCFG */

	tx4927_wdr_init();

	/* clear BusErrorOnWrite flag (W1C) */

	tx4927_ccfg_set(TX4927_CCFG_BEOW);

	/* enable Timeout BusError */

	if (txx9_ccfg_toeon)

		tx4927_ccfg_set(TX4927_CCFG_TOE);



	/* DMA selection */

	txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_DMASEL_ALL);



	/* Use external clock for external arbiter */

	if (!(____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB))

		txx9_clear64(&tx4927_ccfgptr->pcfg, TX4927_PCFG_PCICLKEN_ALL);



	printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",

	       txx9_pcode_str,

	       (cpuclk + 500000) / 1000000,

	       (txx9_master_clock + 500000) / 1000000,

	       (__u32)____raw_readq(&tx4927_ccfgptr->crir),

	       (unsigned long long)____raw_readq(&tx4927_ccfgptr->ccfg),

	       (unsigned long long)____raw_readq(&tx4927_ccfgptr->pcfg));



	printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);

	for (i = 0; i < 4; i++) {

		__u64 cr = TX4927_SDRAMC_CR(i);

		unsigned long base, size;

		if (!((__u32)cr & 0x00000400))

			continue;	/* disabled */

		base = (unsigned long)(cr >> 49) << 21;

		size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21;

		printk(" CR%d:%016llx", i, (unsigned long long)cr);

		tx4927_sdram_resource[i].name = "SDRAM";

		tx4927_sdram_resource[i].start = base;

		tx4927_sdram_resource[i].end = base + size - 1;

		tx4927_sdram_resource[i].flags = IORESOURCE_MEM;

		request_resource(&iomem_resource, &tx4927_sdram_resource[i]);

	}

	printk(" TR:%09llx\n",

	       (unsigned long long)____raw_readq(&tx4927_sdramcptr->tr));



	/* TMR */

	/* disable all timers */

	for (i = 0; i < TX4927_NR_TMR; i++)

		txx9_tmr_init(TX4927_TMR_REG(i) & 0xfffffffffULL);



	/* PIO */

	txx9_gpio_init(TX4927_PIO_REG & 0xfffffffffULL, 0, TX4927_NUM_PIO);

	__raw_writel(0, &tx4927_pioptr->maskcpu);

	__raw_writel(0, &tx4927_pioptr->maskext);

}



void __init tx4927_time_init(unsigned int tmrnr)

{

	if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)

		txx9_clockevent_init(TX4927_TMR_REG(tmrnr) & 0xfffffffffULL,

				     TXX9_IRQ_BASE + TX4927_IR_TMR(tmrnr),

				     TXX9_IMCLK);

}



void __init tx4927_setup_serial(void)

{

#ifdef CONFIG_SERIAL_TXX9

	int i;

	struct uart_port req;



	for (i = 0; i < 2; i++) {

		memset(&req, 0, sizeof(req));

		req.line = i;

		req.iotype = UPIO_MEM;

		req.membase = (unsigned char __iomem *)TX4927_SIO_REG(i);

		req.mapbase = TX4927_SIO_REG(i) & 0xfffffffffULL;

		req.irq = TXX9_IRQ_BASE + TX4927_IR_SIO(i);

		req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;

		req.uartclk = TXX9_IMCLK;

		early_serial_txx9_setup(&req);

	}

#endif /* CONFIG_SERIAL_TXX9 */

}

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