Commit 948e0684 authored by Sylwester Nawrocki's avatar Sylwester Nawrocki
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clk: samsung: exynos5420: Add more entries to EPLL rate table 



Adding these EPLL output frequency entries allows to support all required
audio sample rates on the CODEC and the HDMI interface on Peach-Pit
Chromebook.

Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
parent 06255a92

drivers/clk/samsung/clk-exynos5420.c

+3 −0
Original line number Diff line number Diff line
@@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { 
	PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),

	PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),

	PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),

	PLL_36XX_RATE(24 * MHZ,  73728000U, 98, 2, 4, 19923),

	PLL_36XX_RATE(24 * MHZ,  67737602U, 90, 2, 4, 20762),

	PLL_36XX_RATE(24 * MHZ,  65536003U, 131, 3, 4, 4719),

	PLL_36XX_RATE(24 * MHZ,  49152000U, 197, 3, 5, -25690),

	PLL_36XX_RATE(24 * MHZ,  45158401U, 90, 3, 4, 20762),

	PLL_36XX_RATE(24 * MHZ,  32768001U, 131, 3, 5, 4719),

};

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