Commit 94783036 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux 

Pull clock layer fixes from Mike Turquette:
 "The fixes for the clock tree are mostly run-time bugs in clock
  drivers.

  The fixes for TI DRA7 remove divide-by-zero errors.  The recently
  merged AT91 clock driver fixes some bad error checking and the QCOM
  driver fix restores audio for that platform, a clear regression.  A
  list iteration bug in the framework core was hit recently and is fixed
  up here.  Finally a compilation warning is fixed for efm32gg, which is
  also a regression fix"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk/efm32gg: fix dt init prototype
  clk: prevent erronous parsing of children during rate change
  clk: rockchip: Fix the clocks for i2c1 and i2c2
  clk: qcom: Fix sdc 144kHz frequency entry
  clk: at91: fix num_parents test in at91sam9260 slow clk implementation
  clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate
  clk: ti: divider: Provide error check for incoming parameters in set_rate
parents e2519c2c 8ce8ebeb

drivers/clk/at91/clk-slow.c

+1 −1
Original line number Diff line number Diff line
@@ -447,7 +447,7 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np, 
	int i;



	num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");

	if (num_parents <= 0 || num_parents > 1)

	if (num_parents != 2)

		return;



	for (i = 0; i < num_parents; ++i) {

drivers/clk/clk-efm32gg.c

+3 −3
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ static struct clk_onecell_data clk_data = { 
	.clk_num = ARRAY_SIZE(clk),

};



static int __init efm32gg_cmu_init(struct device_node *np)

static void __init efm32gg_cmu_init(struct device_node *np)

{

	int i;

	void __iomem *base;
@@ -33,7 +33,7 @@ static int __init efm32gg_cmu_init(struct device_node *np) 
	base = of_iomap(np, 0);

	if (!base) {

		pr_warn("Failed to map address range for efm32gg,cmu node\n");

		return -EADDRNOTAVAIL;

		return;

	}



	clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL,
@@ -76,6 +76,6 @@ static int __init efm32gg_cmu_init(struct device_node *np) 
	clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0",

			"HFXO", 0, base + CMU_HFPERCLKEN0, 17, 0, NULL);



	return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);

}

CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);

drivers/clk/clk.c

+6 −1
Original line number Diff line number Diff line
@@ -1467,6 +1467,7 @@ static struct clk *clk_propagate_rate_change(struct clk *clk, unsigned long even 
static void clk_change_rate(struct clk *clk)

{

	struct clk *child;

	struct hlist_node *tmp;

	unsigned long old_rate;

	unsigned long best_parent_rate = 0;

	bool skip_set_rate = false;
@@ -1502,7 +1503,11 @@ static void clk_change_rate(struct clk *clk) 
	if (clk->notifier_count && old_rate != clk->rate)

		__clk_notify(clk, POST_RATE_CHANGE, old_rate, clk->rate);



	hlist_for_each_entry(child, &clk->children, child_node) {

	/*

	 * Use safe iteration, as change_rate can actually swap parents

	 * for certain clock types.

	 */

	hlist_for_each_entry_safe(child, tmp, &clk->children, child_node) {

		/* Skip children who will be reparented to another clock */

		if (child->new_parent && child->new_parent != clk)

			continue;

drivers/clk/qcom/gcc-ipq806x.c

+1 −1
Original line number Diff line number Diff line
@@ -1095,7 +1095,7 @@ static struct clk_branch prng_clk = { 
};



static const struct freq_tbl clk_tbl_sdc[] = {

	{    144000, P_PXO,   5, 18,625 },

	{    200000, P_PXO,   2, 2, 125 },

	{    400000, P_PLL8,  4, 1, 240 },

	{  16000000, P_PLL8,  4, 1,   6 },

	{  17070000, P_PLL8,  1, 2,  45 },

drivers/clk/rockchip/clk-rk3288.c

+2 −2
Original line number Diff line number Diff line
@@ -545,7 +545,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),

	GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),

	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),

	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),

	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),

	GATE(0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),

	GATE(0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),

	GATE(0, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
@@ -603,7 +603,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = { 
	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),

	GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),

	GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),

	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),

	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),

	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),

	GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),

	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),

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