drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array (946a4d5b) · Commits · 戴 / test

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+19 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1428,6 +1428,23 @@ typedef void (amdgpu_wreg_t)(struct amdgpu_device, uint32_t, uint32_t);
	typedef uint32_t (amdgpu_block_rreg_t)(struct amdgpu_device, uint32_t, uint32_t);		typedef uint32_t (amdgpu_block_rreg_t)(struct amdgpu_device, uint32_t, uint32_t);
	typedef void (amdgpu_block_wreg_t)(struct amdgpu_device, uint32_t, uint32_t, uint32_t);		typedef void (amdgpu_block_wreg_t)(struct amdgpu_device, uint32_t, uint32_t, uint32_t);


			/*
			* amdgpu nbio functions
			*
			* Fix me :
			* Put more NBIO specifc func wraper here , for now just try to minimize the
			* change to avoid use SOC15_REG_OFFSET in the constant array
			*/

			struct amdgpu_nbio_funcs {
			u32 (get_hdp_flush_req_offset)(struct amdgpu_device);
			u32 (get_hdp_flush_done_offset)(struct amdgpu_device);
			u32 (get_pcie_index_offset)(struct amdgpu_device);
			u32 (get_pcie_data_offset)(struct amdgpu_device);
			};


	/* Define the HW IP blocks will be used in driver , add more if necessary */		/* Define the HW IP blocks will be used in driver , add more if necessary */
	enum amd_hw_ip_block_type {		enum amd_hw_ip_block_type {
	GC_HWIP = 1,		GC_HWIP = 1,
	@@ -1647,6 +1664,8 @@ struct amdgpu_device {
	/* soc15 register offset based on ip, instance and segment */		/* soc15 register offset based on ip, instance and segment */
	uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];		uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];

			const struct amdgpu_nbio_funcs *nbio_funcs;

	/* delayed work_func for deferring clockgating during resume */		/* delayed work_func for deferring clockgating during resume */
	struct delayed_work late_init_work;		struct delayed_work late_init_work;

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+84 −149

Original line number	Original line	Diff line number	Diff line
	@@ -65,152 +65,84 @@ MODULE_FIRMWARE("amdgpu/raven_mec.bin");
	MODULE_FIRMWARE("amdgpu/raven_mec2.bin");		MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
	MODULE_FIRMWARE("amdgpu/raven_rlc.bin");		MODULE_FIRMWARE("amdgpu/raven_rlc.bin");

	static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =		static const struct soc15_reg_golden golden_settings_gc_9_0[] =
	{		{
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },		SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },		SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),		SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14) },
	{ SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
	SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15),
	SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15) }
	};

	static const u32 golden_settings_gc_9_0[] =
	{
	SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
	SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
	SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
	SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), 0x00001000, 0x00001000,
	SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
	SOC15_REG_OFFSET(GC, 0, mmSQC_CONFIG), 0x03000000, 0x020a2000,
	SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
	SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
	SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
	SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
	};		};

	static const u32 golden_settings_gc_9_0_vg10[] =		static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
	{		{
	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
	SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800)
	};		};

	static const u32 golden_settings_gc_9_1[] =		static const struct soc15_reg_golden golden_settings_gc_9_1[] =
	{		{
	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
	SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
	SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
	SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
	SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
	SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
	SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
	SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
	SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080		SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
	};		};

	static const u32 golden_settings_gc_9_1_rv1[] =		static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
	{		{
	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
	SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
	SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800		SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
	};		};

	static const u32 golden_settings_gc_9_x_common[] =		static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
	{		{
	SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_INDEX), 0xffffffff, 0x00000000,		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
	SOC15_REG_OFFSET(GC, 0, mmGRBM_CAM_DATA), 0xffffffff, 0x2544c382		SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
	};		};

	#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042		#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
	@@ -230,18 +162,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
	{		{
	switch (adev->asic_type) {		switch (adev->asic_type) {
	case CHIP_VEGA10:		case CHIP_VEGA10:
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_gc_9_0,		golden_settings_gc_9_0,
	ARRAY_SIZE(golden_settings_gc_9_0));		ARRAY_SIZE(golden_settings_gc_9_0));
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_gc_9_0_vg10,		golden_settings_gc_9_0_vg10,
	ARRAY_SIZE(golden_settings_gc_9_0_vg10));		ARRAY_SIZE(golden_settings_gc_9_0_vg10));
	break;		break;
	case CHIP_RAVEN:		case CHIP_RAVEN:
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_gc_9_1,		golden_settings_gc_9_1,
	ARRAY_SIZE(golden_settings_gc_9_1));		ARRAY_SIZE(golden_settings_gc_9_1));
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_gc_9_1_rv1,		golden_settings_gc_9_1_rv1,
	ARRAY_SIZE(golden_settings_gc_9_1_rv1));		ARRAY_SIZE(golden_settings_gc_9_1_rv1));
	break;		break;
	@@ -249,7 +181,7 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
	break;		break;
	}		}

	amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common,		soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
	(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));		(const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
	}		}

	@@ -1137,7 +1069,7 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
	adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);		adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
	adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;		adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
	adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;		adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
	adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;		adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
	adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;		adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;

	/* Primitive Buffer */		/* Primitive Buffer */
	@@ -1243,7 +1175,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
	}		}

	gfx_v9_0_write_data_to_reg(ring, 0, false,		gfx_v9_0_write_data_to_reg(ring, 0, false,
	amdgpu_gds_reg_offset[0].mem_size,		SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
	(adev->gds.mem.total_size +		(adev->gds.mem.total_size +
	adev->gfx.ngg.gds_reserve_size) >>		adev->gfx.ngg.gds_reserve_size) >>
	AMDGPU_GDS_SHIFT);		AMDGPU_GDS_SHIFT);
	@@ -1259,7 +1191,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)


	gfx_v9_0_write_data_to_reg(ring, 0, false,		gfx_v9_0_write_data_to_reg(ring, 0, false,
	amdgpu_gds_reg_offset[0].mem_size, 0);		SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);

	amdgpu_ring_commit(ring);		amdgpu_ring_commit(ring);

	@@ -3146,6 +3078,8 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
	uint32_t gws_base, uint32_t gws_size,		uint32_t gws_base, uint32_t gws_size,
	uint32_t oa_base, uint32_t oa_size)		uint32_t oa_base, uint32_t oa_size)
	{		{
			struct amdgpu_device *adev = ring->adev;

	gds_base = gds_base >> AMDGPU_GDS_SHIFT;		gds_base = gds_base >> AMDGPU_GDS_SHIFT;
	gds_size = gds_size >> AMDGPU_GDS_SHIFT;		gds_size = gds_size >> AMDGPU_GDS_SHIFT;

	@@ -3157,22 +3091,22 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,

	/* GDS Base */		/* GDS Base */
	gfx_v9_0_write_data_to_reg(ring, 0, false,		gfx_v9_0_write_data_to_reg(ring, 0, false,
	amdgpu_gds_reg_offset[vmid].mem_base,		SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
	gds_base);		gds_base);

	/* GDS Size */		/* GDS Size */
	gfx_v9_0_write_data_to_reg(ring, 0, false,		gfx_v9_0_write_data_to_reg(ring, 0, false,
	amdgpu_gds_reg_offset[vmid].mem_size,		SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
	gds_size);		gds_size);

	/* GWS */		/* GWS */
	gfx_v9_0_write_data_to_reg(ring, 0, false,		gfx_v9_0_write_data_to_reg(ring, 0, false,
	amdgpu_gds_reg_offset[vmid].gws,		SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
	gws_size << GDS_GWS_VMID0__SIZE__SHIFT \| gws_base);		gws_size << GDS_GWS_VMID0__SIZE__SHIFT \| gws_base);

	/* OA */		/* OA */
	gfx_v9_0_write_data_to_reg(ring, 0, false,		gfx_v9_0_write_data_to_reg(ring, 0, false,
	amdgpu_gds_reg_offset[vmid].oa,		SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
	(1 << (oa_size + oa_base)) - (1 << oa_base));		(1 << (oa_size + oa_base)) - (1 << oa_base));
	}		}

	@@ -3617,6 +3551,7 @@ static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)

	static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)		static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
	{		{
			struct amdgpu_device *adev = ring->adev;
	u32 ref_and_mask, reg_mem_engine;		u32 ref_and_mask, reg_mem_engine;
	const struct nbio_hdp_flush_reg *nbio_hf_reg;		const struct nbio_hdp_flush_reg *nbio_hf_reg;

	@@ -3643,8 +3578,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
	}		}

	gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,		gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
	nbio_hf_reg->hdp_flush_req_offset,		adev->nbio_funcs->get_hdp_flush_req_offset(adev),
	nbio_hf_reg->hdp_flush_done_offset,		adev->nbio_funcs->get_hdp_flush_done_offset(adev),
	ref_and_mask, ref_and_mask, 0x20);		ref_and_mask, ref_and_mask, 0x20);
	}		}

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+11 −9

Original line number	Original line	Diff line number	Diff line
	@@ -35,6 +35,7 @@
	#include "mmhub/mmhub_1_0_offset.h"		#include "mmhub/mmhub_1_0_offset.h"
	#include "athub/athub_1_0_offset.h"		#include "athub/athub_1_0_offset.h"

			#include "soc15.h"
	#include "soc15_common.h"		#include "soc15_common.h"
	#include "umc/umc_6_0_sh_mask.h"		#include "umc/umc_6_0_sh_mask.h"

	@@ -74,16 +75,16 @@ static const u32 golden_settings_vega10_hdp[] =
	0xf6e, 0x0fffffff, 0x00000000,		0xf6e, 0x0fffffff, 0x00000000,
	};		};

	static const u32 golden_settings_mmhub_1_0_0[] =		static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
	{		{
	SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,		SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
	SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565		SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
	};		};

	static const u32 golden_settings_athub_1_0_0[] =		static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
	{		{
	SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,		SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
	SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008		SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
	};		};

	/* Ecc related register addresses, (BASE + reg offset) */		/* Ecc related register addresses, (BASE + reg offset) */
	@@ -883,17 +884,18 @@ static int gmc_v9_0_sw_fini(void *handle)

	static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)		static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
	{		{

	switch (adev->asic_type) {		switch (adev->asic_type) {
	case CHIP_VEGA10:		case CHIP_VEGA10:
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_mmhub_1_0_0,		golden_settings_mmhub_1_0_0,
	ARRAY_SIZE(golden_settings_mmhub_1_0_0));		ARRAY_SIZE(golden_settings_mmhub_1_0_0));
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_athub_1_0_0,		golden_settings_athub_1_0_0,
	ARRAY_SIZE(golden_settings_athub_1_0_0));		ARRAY_SIZE(golden_settings_athub_1_0_0));
	break;		break;
	case CHIP_RAVEN:		case CHIP_RAVEN:
	amdgpu_program_register_sequence(adev,		soc15_program_register_sequence(adev,
	golden_settings_athub_1_0_0,		golden_settings_athub_1_0_0,
	ARRAY_SIZE(golden_settings_athub_1_0_0));		ARRAY_SIZE(golden_settings_athub_1_0_0));
	break;		break;

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

+32 −13

Original line number	Original line	Diff line number	Diff line
	@@ -76,16 +76,13 @@ u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
	return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);		return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
	}		}

	static const u32 nbio_sdma_doorbell_range_reg[] =
	{
	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE),
	SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE)
	};

	void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,		void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
	bool use_doorbell, int doorbell_index)		bool use_doorbell, int doorbell_index)
	{		{
	u32 doorbell_range = RREG32(nbio_sdma_doorbell_range_reg[instance]);		u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
			SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);

			u32 doorbell_range = RREG32(reg);

	if (use_doorbell) {		if (use_doorbell) {
	doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
	@@ -93,7 +90,8 @@ void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
	} else		} else
	doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);		doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);

	WREG32(nbio_sdma_doorbell_range_reg[instance], doorbell_range);		WREG32(reg, doorbell_range);

	}		}

	void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,		void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
	@@ -215,9 +213,27 @@ void nbio_v6_1_get_clockgating_state(struct amdgpu_device adev, u32 flags)
	*flags \|= AMD_CG_SUPPORT_BIF_LS;		*flags \|= AMD_CG_SUPPORT_BIF_LS;
	}		}

			static u32 get_hdp_flush_req_offset(struct amdgpu_device *adev)
			{
			return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
			}

			static u32 get_hdp_flush_done_offset(struct amdgpu_device *adev)
			{
			return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
			}

			static u32 get_pcie_index_offset(struct amdgpu_device *adev)
			{
			return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
			}

			static u32 get_pcie_data_offset(struct amdgpu_device *adev)
			{
			return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
			}

	const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {		const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
	.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ),
	.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE),
	.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,		.ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
	.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,		.ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
	.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,		.ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
	@@ -232,11 +248,14 @@ const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
	.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK		.ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
	};		};

	const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data = {		const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
	.index_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX),		.get_hdp_flush_req_offset = get_hdp_flush_req_offset,
	.data_offset = SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA),		.get_hdp_flush_done_offset = get_hdp_flush_done_offset,
			.get_pcie_index_offset = get_pcie_index_offset,
			.get_pcie_data_offset = get_pcie_data_offset,
	};		};


	void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)		void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
	{		{
	uint32_t reg;		uint32_t reg;

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -27,7 +27,8 @@
	#include "soc15_common.h"		#include "soc15_common.h"

	extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;		extern const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg;
	extern const struct nbio_pcie_index_data nbio_v6_1_pcie_index_data;		extern const struct amdgpu_nbio_funcs nbio_v6_1_funcs;

	int nbio_v6_1_init(struct amdgpu_device *adev);		int nbio_v6_1_init(struct amdgpu_device *adev);
	u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,		u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
	uint32_t idx);		uint32_t idx);

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