drm/mediatek: add YUYV/UYVY color format support for RDMA (94420a63) · Commits · 戴 / test

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

+20 −0

Original line number	Diff line number	Diff line
		@@ -33,6 +33,9 @@
		#define RDMA_ENGINE_EN BIT(0)
		#define RDMA_MODE_MEMORY BIT(1)
		#define DISP_REG_RDMA_SIZE_CON_0 0x0014
		#define RDMA_MATRIX_ENABLE BIT(17)
		#define RDMA_MATRIX_INT_MTX_SEL GENMASK(23, 20)
		#define RDMA_MATRIX_INT_MTX_BT601_to_RGB (6 << 20)
		#define DISP_REG_RDMA_SIZE_CON_1 0x0018
		#define DISP_REG_RDMA_TARGET_LINE 0x001c
		#define DISP_RDMA_MEM_CON 0x0024
		@@ -40,6 +43,8 @@
		#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
		#define MEM_MODE_INPUT_FORMAT_RGBA8888 (0x002 << 4)
		#define MEM_MODE_INPUT_FORMAT_ARGB8888 (0x003 << 4)
		#define MEM_MODE_INPUT_FORMAT_UYVY (0x004 << 4)
		#define MEM_MODE_INPUT_FORMAT_YUYV (0x005 << 4)
		#define MEM_MODE_INPUT_SWAP BIT(8)
		#define DISP_RDMA_MEM_SRC_PITCH 0x002c
		#define DISP_RDMA_MEM_GMC_SETTING_0 0x0030
		@@ -180,6 +185,10 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
		case DRM_FORMAT_XBGR8888:
		case DRM_FORMAT_ABGR8888:
		return MEM_MODE_INPUT_FORMAT_RGBA8888 \| MEM_MODE_INPUT_SWAP;
		case DRM_FORMAT_UYVY:
		return MEM_MODE_INPUT_FORMAT_UYVY;
		case DRM_FORMAT_YUYV:
		return MEM_MODE_INPUT_FORMAT_YUYV;
		}
		}

		@@ -196,6 +205,17 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
		con = rdma_fmt_convert(rdma, fmt);
		writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);

		if (fmt == DRM_FORMAT_UYVY \|\| fmt == DRM_FORMAT_YUYV) {
		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
		RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);
		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
		RDMA_MATRIX_INT_MTX_SEL,
		RDMA_MATRIX_INT_MTX_BT601_to_RGB);
		} else {
		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
		RDMA_MATRIX_ENABLE, 0);
		}

		writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
		writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
		writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);

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