Commit 9420f1ce authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "This is the bulk of the pin control changes for the v5.9 kernel
  series:

  Core changes:

   - The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
     macro" was put in an immutable branch and merged into the pinctrl
     tree as well. We see these changes also here.

   - Improved debug output for pins used as GPIO.

  New drivers:

   - Ocelot Sparx5 SoC driver.

   - Intel Emmitsburg SoC subdriver.

   - Intel Tiger Lake-H SoC subdriver.

   - Qualcomm PM660 SoC subdriver.

   - Renesas SH-PFC R8A774E1 subdriver.

  Driver improvements:

   - Linear improvement and cleanups of the Intel drivers for
     Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
     things.

   - Renesas SH-PFC has added support for RPC pins, groups, and
     functions to r8a77970 and r8a77980.

   - The newere Freescale (now NXP) i.MX8 pin controllers have been
     modularized. This is driven by the Google Android GKI initiative I
     think.

   - Open drain support for pins on the Qualcomm IPQ4019.

   - The Ingenic driver can handle both edges IRQ detection.

   - A big slew of documentation fixes all over the place.

   - A few irqchip template conversions by yours truly.

* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
  dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
  pinctrl: stmfx: Use irqchip template
  pinctrl: amd: Use irqchip template
  pinctrl: mediatek: fix build for tristate changes
  pinctrl: samsung: Use bank name as irqchip name
  pinctrl: core: print gpio in pins debugfs file
  pinctrl: mediatek: add mt6779 eint support
  pinctrl: mediatek: add pinctrl support for MT6779 SoC
  pinctrl: mediatek: avoid virtual gpio trying to set reg
  pinctrl: mediatek: update pinmux definitions for mt6779
  pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
  pinctrl: mcp23s08: Use irqchip template
  pinctrl: sx150x: Use irqchip template
  dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
  pinctrl: intel: Add Intel Emmitsburg pin controller support
  pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
  Revert "gpio: omap: handle pin config bias flags"
  pinctrl: single: Use fallthrough pseudo-keyword
  pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
  pinctrl: baytrail: Use fallthrough pseudo-keyword
  ...
parents dec1fbbc 7ee193e2

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt

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Ingenic XBurst pin controller



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may

be used as GPIOs, multiplexed device functions are configured within the

GPIO port configuration registers and it is typical to refer to pins using the

naming scheme "PxN" where x is a character identifying the GPIO port with

which the pin is associated and N is an integer from 0 to 31 identifying the

pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and

PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830

contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the

jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.





Required properties:

--------------------



 - compatible: One of:

    - "ingenic,jz4740-pinctrl"

    - "ingenic,jz4725b-pinctrl"

    - "ingenic,jz4760-pinctrl"

    - "ingenic,jz4760b-pinctrl"

    - "ingenic,jz4770-pinctrl"

    - "ingenic,jz4780-pinctrl"

    - "ingenic,x1000-pinctrl"

    - "ingenic,x1000e-pinctrl"

    - "ingenic,x1500-pinctrl"

    - "ingenic,x1830-pinctrl"

 - reg: Address range of the pinctrl registers.





Required properties for sub-nodes (GPIO chips):

-----------------------------------------------



 - compatible: Must contain one of:

    - "ingenic,jz4740-gpio"

    - "ingenic,jz4760-gpio"

    - "ingenic,jz4770-gpio"

    - "ingenic,jz4780-gpio"

    - "ingenic,x1000-gpio"

    - "ingenic,x1830-gpio"

 - reg: The GPIO bank number.

 - interrupt-controller: Marks the device node as an interrupt controller.

 - interrupts: Interrupt specifier for the controllers interrupt.

 - #interrupt-cells: Should be 2. Refer to

   ../interrupt-controller/interrupts.txt for more details.

 - gpio-controller: Marks the device node as a GPIO controller.

 - #gpio-cells: Should be 2. The first cell is the GPIO number and the second

    cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the

    GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.

 - gpio-ranges: Range of pins managed by the GPIO controller. Refer to

   ../gpio/gpio.txt for more details.





Example:

--------



pinctrl: pin-controller@10010000 {

	compatible = "ingenic,jz4740-pinctrl";

	reg = <0x10010000 0x400>;

	#address-cells = <1>;

	#size-cells = <0>;



	gpa: gpio@0 {

		compatible = "ingenic,jz4740-gpio";

		reg = <0>;



		gpio-controller;

		gpio-ranges = <&pinctrl 0 0 32>;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;



		interrupt-parent = <&intc>;

		interrupts = <28>;

	};

};

Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Ingenic SoCs pin controller devicetree bindings



description: >

  Please refer to pinctrl-bindings.txt in this directory for details of the

  common pinctrl bindings used by client devices, including the meaning of the

  phrase "pin configuration node".



  For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins

  may be used as GPIOs, multiplexed device functions are configured within the

  GPIO port configuration registers and it is typical to refer to pins using the

  naming scheme "PxN" where x is a character identifying the GPIO port with

  which the pin is associated and N is an integer from 0 to 31 identifying the

  pin within that GPIO port. For example PA0 is the first pin in GPIO port A,

  and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830

  contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the

  JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192

  pins.



maintainers:

  - Paul Cercueil <paul@crapouillou.net>



properties:

  nodename:

    pattern: "^pinctrl@[0-9a-f]+$"



  compatible:

    oneOf:

      - enum:

        - ingenic,jz4740-pinctrl

        - ingenic,jz4725b-pinctrl

        - ingenic,jz4760-pinctrl

        - ingenic,jz4770-pinctrl

        - ingenic,jz4780-pinctrl

        - ingenic,x1000-pinctrl

        - ingenic,x1500-pinctrl

        - ingenic,x1830-pinctrl

      - items:

        - const: ingenic,jz4760b-pinctrl

        - const: ingenic,jz4760-pinctrl

      - items:

        - const: ingenic,x1000e-pinctrl

        - const: ingenic,x1000-pinctrl



  reg:

    maxItems: 1



  "#address-cells":

    const: 1



  "#size-cells":

    const: 0



patternProperties:

  "^gpio@[0-9]$":

    type: object

    properties:

      compatible:

        enum:

          - ingenic,jz4740-gpio

          - ingenic,jz4725b-gpio

          - ingenic,jz4760-gpio

          - ingenic,jz4770-gpio

          - ingenic,jz4780-gpio

          - ingenic,x1000-gpio

          - ingenic,x1500-gpio

          - ingenic,x1830-gpio



      reg:

        items:

          - description: The GPIO bank number



      gpio-controller: true



      "#gpio-cells":

        const: 2



      gpio-ranges:

        maxItems: 1



      interrupt-controller: true



      "#interrupt-cells":

        const: 2

        description:

          Refer to ../interrupt-controller/interrupts.txt for more details.



      interrupts:

        maxItems: 1



    required:

      - compatible

      - reg

      - gpio-controller

      - "#gpio-cells"

      - interrupts

      - interrupt-controller

      - "#interrupt-cells"



    additionalProperties: false



required:

  - compatible

  - reg

  - "#address-cells"

  - "#size-cells"



additionalProperties:

  anyOf:

    - type: object

      allOf:

        - $ref: pincfg-node.yaml#

        - $ref: pinmux-node.yaml#



      properties:

        phandle: true

        function: true

        groups: true

        pins: true

        bias-disable: true

        bias-pull-up: true

        bias-pull-down: true

        output-low: true

        output-high: true

      additionalProperties: false



    - type: object

      properties:

        phandle: true

      additionalProperties:

        type: object

        allOf:

          - $ref: pincfg-node.yaml#

          - $ref: pinmux-node.yaml#



        properties:

          phandle: true

          function: true

          groups: true

          pins: true

          bias-disable: true

          bias-pull-up: true

          bias-pull-down: true

          output-low: true

          output-high: true

        additionalProperties: false



examples:

  - |

    pin-controller@10010000 {

      compatible = "ingenic,jz4770-pinctrl";

      reg = <0x10010000 0x600>;



      #address-cells = <1>;

      #size-cells = <0>;



      gpio@0 {

        compatible = "ingenic,jz4770-gpio";

        reg = <0>;



        gpio-controller;

        gpio-ranges = <&pinctrl 0 0 32>;

        #gpio-cells = <2>;



        interrupt-controller;

        #interrupt-cells = <2>;



        interrupt-parent = <&intc>;

        interrupts = <17>;

      };

    };

Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek MT6779 Pin Controller Device Tree Bindings



maintainers:

  - Andy Teng <andy.teng@mediatek.com>



description: |+

  The pin controller node should be the child of a syscon node with the

  required property:

  - compatible: "syscon"



properties:

  compatible:

    const: mediatek,mt6779-pinctrl



  reg:

    minItems: 9

    maxItems: 9



  reg-names:

    items:

      - const: "gpio"

      - const: "iocfg_rm"

      - const: "iocfg_br"

      - const: "iocfg_lm"

      - const: "iocfg_lb"

      - const: "iocfg_rt"

      - const: "iocfg_lt"

      - const: "iocfg_tl"

      - const: "eint"



  gpio-controller: true



  "#gpio-cells":

    const: 2

    description: |

      Number of cells in GPIO specifier. Since the generic GPIO

      binding is used, the amount of cells must be specified as 2. See the below

      mentioned gpio binding representation for description of particular cells.



  gpio-ranges:

    minItems: 1

    maxItems: 5

    description: |

      GPIO valid number range.



  interrupt-controller: true



  interrupts:

    maxItems: 1

    description: |

      Specifies the summary IRQ.



  "#interrupt-cells":

    const: 2



required:

  - compatible

  - reg

  - reg-names

  - gpio-controller

  - "#gpio-cells"

  - gpio-ranges

  - interrupt-controller

  - interrupts

  - "#interrupt-cells"



patternProperties:

  '-[0-9]*$':

    type: object

    patternProperties:

      '-pins*$':

        type: object

        description: |

          A pinctrl node should contain at least one subnodes representing the

          pinctrl groups available on the machine. Each subnode will list the

          pins it needs, and how they should be configured, with regard to muxer

          configuration, pullups, drive strength, input enable/disable and input schmitt.

        $ref: "/schemas/pinctrl/pincfg-node.yaml"



        properties:

          pinmux:

            description:

              integer array, represents gpio pin number and mux setting.

              Supported pin number and mux varies for different SoCs, and are defined

              as macros in boot/dts/<soc>-pinfunc.h directly.



          bias-disable: true



          bias-pull-up: true



          bias-pull-down: true



          input-enable: true



          input-disable: true



          output-low: true



          output-high: true



          input-schmitt-enable: true



          input-schmitt-disable: true



          mediatek,pull-up-adv:

            description: |

              Pull up setings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3]



          mediatek,pull-down-adv:

            description: |

              Pull down settings for 2 pull resistors, R0 and R1. User can

              configure those special pins. Valid arguments are described as below:

              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.

              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.

              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.

              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.

            $ref: /schemas/types.yaml#/definitions/uint32

            enum: [0, 1, 2, 3]



        required:

          - pinmux



        additionalProperties: false



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/pinctrl/mt6779-pinfunc.h>



    soc {

        #address-cells = <2>;

        #size-cells = <2>;



        pio: pinctrl@10005000 {

            compatible = "mediatek,mt6779-pinctrl";

            reg = <0 0x10005000 0 0x1000>,

                <0 0x11c20000 0 0x1000>,

                <0 0x11d10000 0 0x1000>,

                <0 0x11e20000 0 0x1000>,

                <0 0x11e70000 0 0x1000>,

                <0 0x11ea0000 0 0x1000>,

                <0 0x11f20000 0 0x1000>,

                <0 0x11f30000 0 0x1000>,

                <0 0x1000b000 0 0x1000>;

            reg-names = "gpio", "iocfg_rm",

              "iocfg_br", "iocfg_lm",

              "iocfg_lb", "iocfg_rt",

              "iocfg_lt", "iocfg_tl",

              "eint";

            gpio-controller;

            #gpio-cells = <2>;

            gpio-ranges = <&pio 0 0 210>;

            interrupt-controller;

            #interrupt-cells = <2>;

            interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;



            mmc0_pins_default: mmc0-0 {

                cmd-dat-pins {

                    pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,

                        <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,

                        <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,

                        <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,

                        <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,

                        <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,

                        <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,

                        <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,

                        <PINMUX_GPIO167__FUNC_MSDC0_CMD>;

                    input-enable;

                    mediatek,pull-up-adv = <1>;

                };

                clk-pins {

                    pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;

                    mediatek,pull-down-adv = <2>;

                };

                rst-pins {

                    pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;

                    mediatek,pull-up-adv = <0>;

                };

            };

        };



        mmc0 {

           pinctrl-0 = <&mmc0_pins_default>;

           pinctrl-names = "default";

        };

    };

Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt

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@@ -44,7 +44,8 @@ information about e.g. the mux function. 


The following generic properties as defined in pinctrl-bindings.txt are valid

to specify in a pin configuration subnode:

 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength.

 pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-open-drain,

 drive-strength.



Non-empty subnodes must specify the 'pins' property.

Note that not all properties are valid for all pins.

Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt

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@@ -23,6 +23,8 @@ PMIC's from Qualcomm. 
		    "qcom,pmi8994-gpio"

		    "qcom,pmi8998-gpio"

		    "qcom,pms405-gpio"

		    "qcom,pm660-gpio"

		    "qcom,pm660l-gpio"

		    "qcom,pm8150-gpio"

		    "qcom,pm8150b-gpio"

		    "qcom,pm6150-gpio"

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