spi: fsl-dspi: Set max_speed_hz for master (9419b200) · Commits · 戴 / test

drivers/spi/spi-fsl-dspi.c

+7 −0

Original line number	Original line	Diff line number	Diff line
	@@ -121,18 +121,22 @@ enum dspi_trans_mode {

	struct fsl_dspi_devtype_data {		struct fsl_dspi_devtype_data {
	enum dspi_trans_mode trans_mode;		enum dspi_trans_mode trans_mode;
			u8 max_clock_factor;
	};		};

	static const struct fsl_dspi_devtype_data vf610_data = {		static const struct fsl_dspi_devtype_data vf610_data = {
	.trans_mode = DSPI_EOQ_MODE,		.trans_mode = DSPI_EOQ_MODE,
			.max_clock_factor = 2,
	};		};

	static const struct fsl_dspi_devtype_data ls1021a_v1_data = {		static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
	.trans_mode = DSPI_TCFQ_MODE,		.trans_mode = DSPI_TCFQ_MODE,
			.max_clock_factor = 8,
	};		};

	static const struct fsl_dspi_devtype_data ls2085a_data = {		static const struct fsl_dspi_devtype_data ls2085a_data = {
	.trans_mode = DSPI_TCFQ_MODE,		.trans_mode = DSPI_TCFQ_MODE,
			.max_clock_factor = 8,
	};		};

	struct fsl_dspi {		struct fsl_dspi {
	@@ -726,6 +730,9 @@ static int dspi_probe(struct platform_device *pdev)
	}		}
	clk_prepare_enable(dspi->clk);		clk_prepare_enable(dspi->clk);

			master->max_speed_hz =
			clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;

	init_waitqueue_head(&dspi->waitq);		init_waitqueue_head(&dspi->waitq);
	platform_set_drvdata(pdev, master);		platform_set_drvdata(pdev, master);