Commit 9413b9a6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-next-msm-5.8-2020-06-08' of git://anongit.freedesktop.org/drm/drm 

Pull drm msm updates from Dave Airlie:
 "This tree has been in next for a couple of weeks, but Rob missed an
  arm32 build issue, so I was awaiting the tree with a patch reverted.

   - new gpu support: a405, a640, a650

   - dpu: color processing support

   - mdp5: support for msm8x36 (the thing with a405)

   - some prep work for per-context pagetables (ie the part that does
     not depend on in-flight iommu patches)

   - last but not least, UABI update for submit ioctl to support syncobj
     (from Bas)"

* tag 'drm-next-msm-5.8-2020-06-08' of git://anongit.freedesktop.org/drm/drm: (30 commits)
  Revert "drm/msm/dpu: add support for clk and bw scaling for display"
  drm/msm/a6xx: skip HFI set freq if GMU is powered down
  drm/msm: Update the MMU helper function APIs
  drm/msm: Refactor address space initialization
  drm/msm: Attach the IOMMU device during initialization
  drm/msm/dpu: dpu_setup_dspp_pcc() can be static
  drm/msm/a6xx: a6xx_hfi_send_start() can be static
  drm/msm/a4xx: add a405_registers for a405 device
  drm/msm/a4xx: add adreno a405 support
  drm/msm/a6xx: update a6xx_hw_init for A640 and A650
  drm/msm/a6xx: enable GMU log
  drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650
  drm/msm/a6xx: A640/A650 GMU firmware path
  drm/msm/a6xx: HFI v2 for A640 and A650
  drm/msm/a6xx: add A640/A650 to gpulist
  drm/msm/a6xx: use msm_gem for GMU memory objects
  drm/msm: add internal MSM_BO_MAP_PRIV flag
  drm/msm: add msm_gem_get_and_pin_iova_range
  drm/msm: Check for powered down HW in the devfreq callbacks
  drm/msm/dpu: update bandwidth threshold check
  ...
parents 10782166 efe792f3

drivers/gpu/drm/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -65,6 +65,7 @@ msm-y := \ 
	disp/dpu1/dpu_hw_lm.o \

	disp/dpu1/dpu_hw_pingpong.o \

	disp/dpu1/dpu_hw_sspp.o \

	disp/dpu1/dpu_hw_dspp.o \

	disp/dpu1/dpu_hw_top.o \

	disp/dpu1/dpu_hw_util.o \

	disp/dpu1/dpu_hw_vbif.o \

drivers/gpu/drm/msm/adreno/a2xx_gpu.c

+16 −0
Original line number Diff line number Diff line
@@ -401,6 +401,21 @@ static struct msm_gpu_state *a2xx_gpu_state_get(struct msm_gpu *gpu) 
	return state;

}



static struct msm_gem_address_space *

a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)

{

	struct msm_mmu *mmu = msm_gpummu_new(&pdev->dev, gpu);

	struct msm_gem_address_space *aspace;



	aspace = msm_gem_address_space_create(mmu, "gpu", SZ_16M,

		SZ_16M + 0xfff * SZ_64K);



	if (IS_ERR(aspace) && !IS_ERR(mmu))

		mmu->funcs->destroy(mmu);



	return aspace;

}



/* Register offset defines for A2XX - copy of A3XX */

static const unsigned int a2xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {

	REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_BASE, REG_AXXX_CP_RB_BASE),
@@ -429,6 +444,7 @@ static const struct adreno_gpu_funcs funcs = { 
#endif

		.gpu_state_get = a2xx_gpu_state_get,

		.gpu_state_put = adreno_gpu_state_put,

		.create_address_space = a2xx_create_address_space,

	},

};

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+1 −0
Original line number Diff line number Diff line
@@ -441,6 +441,7 @@ static const struct adreno_gpu_funcs funcs = { 
#endif

		.gpu_state_get = a3xx_gpu_state_get,

		.gpu_state_put = adreno_gpu_state_put,

		.create_address_space = adreno_iommu_create_address_space,

	},

};

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+68 −15
Original line number Diff line number Diff line
@@ -66,6 +66,8 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) 
		}

	}



	/* No CCU for A405 */

	if (!adreno_is_a405(adreno_gpu)) {

		for (i = 0; i < 4; i++) {

			gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i),

					0x00000922);
@@ -80,6 +82,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) 
			gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i),

					0x00000001);

		}

	}



	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_MODE_GPC, 0x02222222);

	gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_GPC, 0x04100104);
@@ -137,7 +140,9 @@ static int a4xx_hw_init(struct msm_gpu *gpu) 
	uint32_t *ptr, len;

	int i, ret;



	if (adreno_is_a420(adreno_gpu)) {

	if (adreno_is_a405(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);

	} else if (adreno_is_a420(adreno_gpu)) {

		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT, 0x0001001F);

		gpu_write(gpu, REG_A4XX_VBIF_ABIT_SORT_CONF, 0x000000A4);

		gpu_write(gpu, REG_A4XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001);
@@ -440,6 +445,52 @@ static const unsigned int a4xx_registers[] = { 
	~0 /* sentinel */

};



static const unsigned int a405_registers[] = {

	/* RBBM */

	0x0000, 0x0002, 0x0004, 0x0021, 0x0023, 0x0024, 0x0026, 0x0026,

	0x0028, 0x002B, 0x002E, 0x0034, 0x0037, 0x0044, 0x0047, 0x0066,

	0x0068, 0x0095, 0x009C, 0x0170, 0x0174, 0x01AF,

	/* CP */

	0x0200, 0x0233, 0x0240, 0x0250, 0x04C0, 0x04DD, 0x0500, 0x050B,

	0x0578, 0x058F,

	/* VSC */

	0x0C00, 0x0C03, 0x0C08, 0x0C41, 0x0C50, 0x0C51,

	/* GRAS */

	0x0C80, 0x0C81, 0x0C88, 0x0C8F,

	/* RB */

	0x0CC0, 0x0CC0, 0x0CC4, 0x0CD2,

	/* PC */

	0x0D00, 0x0D0C, 0x0D10, 0x0D17, 0x0D20, 0x0D23,

	/* VFD */

	0x0E40, 0x0E4A,

	/* VPC */

	0x0E60, 0x0E61, 0x0E63, 0x0E68,

	/* UCHE */

	0x0E80, 0x0E84, 0x0E88, 0x0E95,

	/* GRAS CTX 0 */

	0x2000, 0x2004, 0x2008, 0x2067, 0x2070, 0x2078, 0x207B, 0x216E,

	/* PC CTX 0 */

	0x21C0, 0x21C6, 0x21D0, 0x21D0, 0x21D9, 0x21D9, 0x21E5, 0x21E7,

	/* VFD CTX 0 */

	0x2200, 0x2204, 0x2208, 0x22A9,

	/* GRAS CTX 1 */

	0x2400, 0x2404, 0x2408, 0x2467, 0x2470, 0x2478, 0x247B, 0x256E,

	/* PC CTX 1 */

	0x25C0, 0x25C6, 0x25D0, 0x25D0, 0x25D9, 0x25D9, 0x25E5, 0x25E7,

	/* VFD CTX 1 */

	0x2600, 0x2604, 0x2608, 0x26A9,

	/* VBIF version 0x20050000*/

	0x3000, 0x3007, 0x302C, 0x302C, 0x3030, 0x3030, 0x3034, 0x3036,

	0x3038, 0x3038, 0x303C, 0x303D, 0x3040, 0x3040, 0x3049, 0x3049,

	0x3058, 0x3058, 0x305B, 0x3061, 0x3064, 0x3068, 0x306C, 0x306D,

	0x3080, 0x3088, 0x308B, 0x308C, 0x3090, 0x3094, 0x3098, 0x3098,

	0x309C, 0x309C, 0x30C0, 0x30C0, 0x30C8, 0x30C8, 0x30D0, 0x30D0,

	0x30D8, 0x30D8, 0x30E0, 0x30E0, 0x3100, 0x3100, 0x3108, 0x3108,

	0x3110, 0x3110, 0x3118, 0x3118, 0x3120, 0x3120, 0x3124, 0x3125,

	0x3129, 0x3129, 0x340C, 0x340C, 0x3410, 0x3410,

	~0 /* sentinel */

};



static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu)

{

	struct msm_gpu_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
@@ -532,6 +583,7 @@ static const struct adreno_gpu_funcs funcs = { 
#endif

		.gpu_state_get = a4xx_gpu_state_get,

		.gpu_state_put = adreno_gpu_state_put,

		.create_address_space = adreno_iommu_create_address_space,

	},

	.get_timestamp = a4xx_get_timestamp,

};
@@ -563,13 +615,14 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev) 
	gpu->perfcntrs = NULL;

	gpu->num_perfcntrs = 0;



	adreno_gpu->registers = a4xx_registers;

	adreno_gpu->reg_offsets = a4xx_register_offsets;



	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);

	if (ret)

		goto fail;



	adreno_gpu->registers = adreno_is_a405(adreno_gpu) ? a405_registers :

							     a4xx_registers;

	adreno_gpu->reg_offsets = a4xx_register_offsets;



	/* if needed, allocate gmem: */

	if (adreno_is_a4xx(adreno_gpu)) {

		ret = adreno_gpu_ocmem_init(dev->dev, adreno_gpu,

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+7 −0
Original line number Diff line number Diff line
@@ -1404,6 +1404,10 @@ static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu) 
{

	u64 busy_cycles, busy_time;



	/* Only read the gpu busy if the hardware is already active */

	if (pm_runtime_get_if_in_use(&gpu->pdev->dev) == 0)

		return 0;



	busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO,

			REG_A5XX_RBBM_PERFCTR_RBBM_0_HI);
@@ -1412,6 +1416,8 @@ static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu) 


	gpu->devfreq.busy_cycles = busy_cycles;



	pm_runtime_put(&gpu->pdev->dev);



	if (WARN_ON(busy_time > ~0LU))

		return ~0LU;
@@ -1439,6 +1445,7 @@ static const struct adreno_gpu_funcs funcs = { 
		.gpu_busy = a5xx_gpu_busy,

		.gpu_state_get = a5xx_gpu_state_get,

		.gpu_state_put = a5xx_gpu_state_put,

		.create_address_space = adreno_iommu_create_address_space,

	},

	.get_timestamp = a5xx_get_timestamp,

};

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