Unverified Commit 9401d5aa authored Mar 06, 2020 by Paul Cercueil Committed by Mark Brown Mar 09, 2020

ASoC: jz4740-i2s: Fix divider written at incorrect offset in register



The 4-bit divider value was written at offset 8, while the jz4740
programming manual locates it at offset 0.

Fixes: 26b0aad8 ("ASoC: jz4740: Add dynamic sampling rate support to jz4740-i2s")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200306222931.39664-2-paul@crapouillou.net


Signed-off-by: Mark Brown <broonie@kernel.org>

parent d902e785

sound/soc/jz4740/jz4740-i2s.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -83,7 +83,7 @@
		#define JZ_AIC_I2S_STATUS_BUSY BIT(2)

		#define JZ_AIC_CLK_DIV_MASK 0xf
		#define I2SDIV_DV_SHIFT 8
		#define I2SDIV_DV_SHIFT 0
		#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
		#define I2SDIV_IDV_SHIFT 8
		#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)

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