Commit 93cc1228 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "The interrupt subsystem delivers this time:

   - Refactoring of the GIC-V3 driver to prepare for the GIC-V4 support

   - Initial GIC-V4 support

   - Consolidation of the FSL MSI support

   - Utilize the effective affinity interface in various ARM irqchip
     drivers

   - Yet another interrupt chip driver (UniPhier AIDET)

   - Bulk conversion of the irq chip driver to use %pOF

   - The usual small fixes and improvements all over the place"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (77 commits)
  irqchip/ls-scfg-msi: Add MSI affinity support
  irqchip/ls-scfg-msi: Add LS1043a v1.1 MSI support
  irqchip/ls-scfg-msi: Add LS1046a MSI support
  arm64: dts: ls1046a: Add MSI dts node
  arm64: dts: ls1043a: Share all MSIs
  arm: dts: ls1021a: Share all MSIs
  arm64: dts: ls1043a: Fix typo of MSI compatible string
  arm: dts: ls1021a: Fix typo of MSI compatible string
  irqchip/ls-scfg-msi: Fix typo of MSI compatible strings
  irqchip/irq-bcm7120-l2: Use correct I/O accessors for irq_fwd_mask
  irqchip/mmp: Make mmp_intc_conf const
  irqchip/gic: Make irq_chip const
  irqchip/gic-v3: Advertise GICv4 support to KVM
  irqchip/gic-v4: Enable low-level GICv4 operations
  irqchip/gic-v4: Add some basic documentation
  irqchip/gic-v4: Add VLPI configuration interface
  irqchip/gic-v4: Add VPE command interface
  irqchip/gic-v4: Add per-VM VPE domain creation
  irqchip/gic-v3-its: Set implementation defined bit to enable VLPIs
  irqchip/gic-v3-its: Allow doorbell interrupts to be injected/cleared
  ...
parents dd90cccf 9fbd7fd2

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt

+5 −3
Original line number Diff line number Diff line
@@ -4,8 +4,10 @@ Required properties: 


- compatible: should be "fsl,<soc-name>-msi" to identify

	      Layerscape PCIe MSI controller block such as:

              "fsl,1s1021a-msi"

              "fsl,1s1043a-msi"

              "fsl,ls1021a-msi"

              "fsl,ls1043a-msi"

              "fsl,ls1046a-msi"

              "fsl,ls1043a-v1.1-msi"

- msi-controller: indicates that this is a PCIe MSI controller node

- reg: physical base address of the controller and length of memory mapped.

- interrupts: an interrupt to the parent interrupt controller.
@@ -23,7 +25,7 @@ MSI controller node 
Examples:



	msi1: msi-controller@1571000 {

		compatible = "fsl,1s1043a-msi";

		compatible = "fsl,ls1043a-msi";

		reg = <0x0 0x1571000 0x0 0x8>,

		msi-controller;

		interrupts = <0 116 0x4>;

Documentation/devicetree/bindings/interrupt-controller/socionext,uniphier-aidet.txt

0 → 100644
+32 −0
Original line number Diff line number Diff line 
UniPhier AIDET



UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic

Interrupt Controller).  GIC itself can handle only high level and rising edge

interrupts.  The AIDET provides logic inverter to support low level and falling

edge interrupts.



Required properties:

- compatible: Should be one of the following:

    "socionext,uniphier-ld4-aidet"  - for LD4 SoC

    "socionext,uniphier-pro4-aidet" - for Pro4 SoC

    "socionext,uniphier-sld8-aidet" - for sLD8 SoC

    "socionext,uniphier-pro5-aidet" - for Pro5 SoC

    "socionext,uniphier-pxs2-aidet" - for PXs2/LD6b SoC

    "socionext,uniphier-ld11-aidet" - for LD11 SoC

    "socionext,uniphier-ld20-aidet" - for LD20 SoC

    "socionext,uniphier-pxs3-aidet" - for PXs3 SoC

- reg: Specifies offset and length of the register set for the device.

- interrupt-controller: Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an interrupt

  source.  The value should be 2.  The first cell defines the interrupt number

  (corresponds to the SPI interrupt number of GIC).  The second cell specifies

  the trigger type as defined in interrupts.txt in this directory.



Example:



	aidet: aidet@5fc20000 {

		compatible = "socionext,uniphier-pro4-aidet";

		reg = <0x5fc20000 0x200>;

		interrupt-controller;

		#interrupt-cells = <2>;

	};

Documentation/driver-model/devres.txt

+1 −0
Original line number Diff line number Diff line
@@ -312,6 +312,7 @@ IRQ 
  devm_irq_alloc_descs_from()

  devm_irq_alloc_generic_chip()

  devm_irq_setup_generic_chip()

  devm_irq_sim_init()



LED

  devm_led_classdev_register()

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1993,6 +1993,7 @@ F: arch/arm64/boot/dts/socionext/ 
F:	drivers/bus/uniphier-system-bus.c

F:	drivers/clk/uniphier/

F:	drivers/i2c/busses/i2c-uniphier*

F:	drivers/irqchip/irq-uniphier-aidet.c

F:	drivers/pinctrl/uniphier/

F:	drivers/reset/reset-uniphier.c

F:	drivers/tty/serial/8250/8250_uniphier.c

arch/arm/boot/dts/ls1021a.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -129,14 +129,14 @@ 
		};



		msi1: msi-controller@1570e00 {

			compatible = "fsl,1s1021a-msi";

			compatible = "fsl,ls1021a-msi";

			reg = <0x0 0x1570e00 0x0 0x8>;

			msi-controller;

			interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

		};



		msi2: msi-controller@1570e08 {

			compatible = "fsl,1s1021a-msi";

			compatible = "fsl,ls1021a-msi";

			reg = <0x0 0x1570e08 0x0 0x8>;

			msi-controller;

			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
@@ -699,7 +699,7 @@ 
			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi1>;

			msi-parent = <&msi1>, <&msi2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
@@ -722,7 +722,7 @@ 
			bus-range = <0x0 0xff>;

			ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */

				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */

			msi-parent = <&msi2>;

			msi-parent = <&msi1>, <&msi2>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 7>;

			interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,

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