Commit 93a4b1b9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 

Pull pin control updates from Linus Walleij:
 "Here is the bulk of pin control changes for the v4.2 series: Quite a
  lot of new SoC subdrivers and two new main drivers this time, apart
  from that business as usual.

  Details:

  Core functionality:
   - Enable exclusive pin ownership: it is possible to flag a pin
     controller so that GPIO and other functions cannot use a single pin
     simultaneously.

  New drivers:
   - NXP LPC18xx System Control Unit pin controller
   - Imagination Pistachio SoC pin controller

  New subdrivers:
   - Freescale i.MX7d SoC
   - Intel Sunrisepoint-H PCH
   - Renesas PFC R8A7793
   - Renesas PFC R8A7794
   - Mediatek MT6397, MT8127
   - SiRF Atlas 7
   - Allwinner A33
   - Qualcomm MSM8660
   - Marvell Armada 395
   - Rockchip RK3368

  Cleanups:
   - A big cleanup of the Marvell MVEBU driver rectifying it to
     correspond to reality
   - Drop platform device probing from the SH PFC driver, we are now a
     DT only shop for SuperH
   - Drop obsolte multi-platform check for SH PFC
   - Various janitorial: constification, grammar etc

  Improvements:
   - The AT91 GPIO portions now supports the set_multiple() feature
   - Split out SPI pins on the Xilinx Zynq
   - Support DTs without specific function nodes in the i.MX driver"

* tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits)
  pinctrl: rockchip: add support for the rk3368
  pinctrl: rockchip: generalize perpin driver-strength setting
  pinctrl: sh-pfc: r8a7794: add SDHI pin groups
  pinctrl: sh-pfc: r8a7794: add MMCIF pin groups
  pinctrl: sh-pfc: add R8A7794 PFC support
  pinctrl: make pinctrl_register() return proper error code
  pinctrl: mvebu: armada-39x: add support for Armada 395 variant
  pinctrl: mvebu: armada-39x: add missing SATA functions
  pinctrl: mvebu: armada-39x: add missing PCIe functions
  pinctrl: mvebu: armada-38x: add ptp functions
  pinctrl: mvebu: armada-38x: add ua1 functions
  pinctrl: mvebu: armada-38x: add nand functions
  pinctrl: mvebu: armada-38x: add sata functions
  pinctrl: mvebu: armada-xp: add dram functions
  pinctrl: mvebu: armada-xp: add nand rb function
  pinctrl: mvebu: armada-xp: add spi1 function
  pinctrl: mvebu: armada-39x: normalize ref clock naming
  pinctrl: mvebu: armada-xp: rename spi to spi0
  pinctrl: mvebu: armada-370: align spi1 clock pin naming
  pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet
  ...
parents d59b92f9 daecdc66

Documentation/devicetree/bindings/gpio/gpio-atlas7.txt

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+50 −0
Original line number Diff line number Diff line 
CSR SiRFatlas7 GPIO controller bindings



Required properties:

- compatible	: "sirf,atlas7-gpio"

- reg		: Address range of the pinctrl registers

- interrupts	: Interrupts used by every GPIO group

- gpio-banks	: How many gpio banks on this controller

- gpio-controller : Indicates this device is a GPIO controller

- interrupt-controller  : Marks the device node as an interrupt controller



The GPIO controller also acts as an interrupt controller. It uses the default

two cells specifier as described in Documentation/devicetree/bindings/

interrupt-controller/interrupts.txt.



Example:



	gpio_0: gpio_mediam@17040000 {

		compatible = "sirf,atlas7-gpio";

		reg = <0x17040000 0x1000>;

		interrupts = <0 13 0>, <0 14 0>;



		#gpio-cells = <2>;

		#interrupt-cells = <2>;



		gpio-controller;

		interrupt-controller;



		gpio-banks = <2>;

		gpio-ranges = <&pinctrl 0 0 0>,

				<&pinctrl 32 0 0>;

		gpio-ranges-group-names = "lvds_gpio_grp",

					"uart_nand_gpio_grp";

	};



	leds {

		compatible = "gpio-leds";



		led1 {

			gpios = <&gpio_1 15 0>;

			...

		};



		led2 {

			gpios = <&gpio_2 34 0>;

			...

		};

	};



Please refer to gpio.txt in this directory for details of the common

gpio properties used by devices.

Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt

+2 −0
Original line number Diff line number Diff line
@@ -16,6 +16,8 @@ Required properties: 
  "allwinner,sun7i-a20-pinctrl"

  "allwinner,sun8i-a23-pinctrl"

  "allwinner,sun8i-a23-r-pinctrl"

  "allwinner,sun8i-a33-pinctrl"



- reg: Should contain the register physical address and length for the

  pin controller.

Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt

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+217 −0
Original line number Diff line number Diff line 
Imagination Technologies Pistachio SoC pin controllers

======================================================



The pin controllers on Pistachio are a combined GPIO controller, (GPIO)

interrupt controller, and pinmux + pinconf device. The system ("east") pin

controller on Pistachio has 99 pins, 90 of which are MFIOs which can be

configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs

each. The GPIO banks are represented as sub-nodes of the pad controller node.



Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and

../interrupt-controller/interrupts.txt for generic information regarding

pin controller, GPIO, and interrupt bindings.



Required properties for pin controller node:

--------------------------------------------

 - compatible: "img,pistachio-system-pinctrl".

 - reg: Address range of the pinctrl registers.



Required properties for GPIO bank sub-nodes:

--------------------------------------------

 - interrupts: Interrupt line for the GPIO bank.

 - gpio-controller: Indicates the device is a GPIO controller.

 - #gpio-cells: Must be two. The first cell is the GPIO pin number and the

   second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for

   a list of possible values.

 - interrupt-controller: Indicates the device is an interrupt controller.

 - #interrupt-cells: Must be two. The first cell is the GPIO pin number and

   the second cell encodes the interrupt flags. See

   <dt-bindings/interrupt-controller/irq.h> for a list of valid flags.



Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.



Required properties for pin configuration sub-nodes:

----------------------------------------------------

 - pins: List of pins to which the configuration applies. See below for a

   list of possible pins.



Optional properties for pin configuration sub-nodes:

----------------------------------------------------

 - function: Mux function for the specified pins. This is not applicable for

   non-MFIO pins. See below for a list of valid functions for each pin.

 - bias-high-impedance: Enable high-impedance mode.

 - bias-pull-up: Enable weak pull-up.

 - bias-pull-down: Enable weak pull-down.

 - bias-bus-hold: Enable bus-keeper mode.

 - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.

 - input-schmitt-enable: Enable Schmitt trigger.

 - input-schmitt-disable: Disable Schmitt trigger.

 - slew-rate: Slew rate control. 0 for slow, 1 for fast.



Pin		Functions

---		---------

mfio0		spim1

mfio1		spim1, spim0, uart1

mfio2		spim1, spim0, uart1

mfio3		spim1

mfio4		spim1

mfio5		spim1

mfio6		spim1

mfio7		spim1

mfio8		spim0

mfio9		spim0

mfio10		spim0

mfio11		spis

mfio12		spis

mfio13		spis

mfio14		spis

mfio15		sdhost, mips_trace_clk, mips_trace_data

mfio16		sdhost, mips_trace_dint, mips_trace_data

mfio17		sdhost, mips_trace_trigout, mips_trace_data

mfio18		sdhost, mips_trace_trigin, mips_trace_data

mfio19		sdhost, mips_trace_dm, mips_trace_data

mfio20		sdhost, mips_trace_probe_n, mips_trace_data

mfio21		sdhost, mips_trace_data

mfio22		sdhost, mips_trace_data

mfio23		sdhost

mfio24		sdhost

mfio25		sdhost

mfio26		sdhost

mfio27		sdhost

mfio28		i2c0, spim0

mfio29		i2c0, spim0

mfio30		i2c1, spim0

mfio31		i2c1, spim1

mfio32		i2c2

mfio33		i2c2

mfio34		i2c3

mfio35		i2c3

mfio36		i2s_out, audio_clk_in

mfio37		i2s_out, debug_raw_cca_ind

mfio38		i2s_out, debug_ed_sec20_cca_ind

mfio39		i2s_out, debug_ed_sec40_cca_ind

mfio40		i2s_out, debug_agc_done_0

mfio41		i2s_out, debug_agc_done_1

mfio42		i2s_out, debug_ed_cca_ind

mfio43		i2s_out, debug_s2l_done

mfio44		i2s_out

mfio45		i2s_dac_clk, audio_sync

mfio46		audio_trigger

mfio47		i2s_in

mfio48		i2s_in

mfio49		i2s_in

mfio50		i2s_in

mfio51		i2s_in

mfio52		i2s_in

mfio53		i2s_in

mfio54		i2s_in, spdif_in

mfio55		uart0, spim0, spim1

mfio56		uart0, spim0, spim1

mfio57		uart0, spim0, spim1

mfio58		uart0, spim1

mfio59		uart1

mfio60		uart1

mfio61		spdif_out

mfio62		spdif_in

mfio63		eth, mips_trace_clk, mips_trace_data

mfio64		eth, mips_trace_dint, mips_trace_data

mfio65		eth, mips_trace_trigout, mips_trace_data

mfio66		eth, mips_trace_trigin, mips_trace_data

mfio67		eth, mips_trace_dm, mips_trace_data

mfio68		eth, mips_trace_probe_n, mips_trace_data

mfio69		eth, mips_trace_data

mfio70		eth, mips_trace_data

mfio71		eth

mfio72		ir

mfio73		pwmpdm, mips_trace_clk, sram_debug

mfio74		pwmpdm, mips_trace_dint, sram_debug

mfio75		pwmpdm, mips_trace_trigout, rom_debug

mfio76		pwmpdm, mips_trace_trigin, rom_debug

mfio77		mdc_debug, mips_trace_dm, rpu_debug

mfio78		mdc_debug, mips_trace_probe_n, rpu_debug

mfio79		ddr_debug, mips_trace_data, mips_debug

mfio80		ddr_debug, mips_trace_data, mips_debug

mfio81		dreq0, mips_trace_data, eth_debug

mfio82		dreq1, mips_trace_data, eth_debug

mfio83		mips_pll_lock, mips_trace_data, usb_debug

mfio84		sys_pll_lock, mips_trace_data, usb_debug

mfio85		wifi_pll_lock, mips_trace_data, sdhost_debug

mfio86		bt_pll_lock, mips_trace_data, sdhost_debug

mfio87		rpu_v_pll_lock, dreq2, socif_debug

mfio88		rpu_l_pll_lock, dreq3, socif_debug

mfio89		audio_pll_lock, dreq4, dreq5

tck

trstn

tdi

tms

tdo

jtag_comply

safe_mode

por_disable

resetn



Example:

--------

pinctrl@18101C00 {

	compatible = "img,pistachio-system-pinctrl";

	reg = <0x18101C00 0x400>;



	gpio0: gpio0 {

		interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;



		gpio-controller;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;

	};



	...



	gpio5: gpio5 {

		interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;



		gpio-controller;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;

	};



	...



	uart0_xfer: uart0-xfer {

		uart0-rxd {

			pins = "mfio55";

			function = "uart0";

		};

		uart0-txd {

			pins = "mfio56";

			function = "uart0";

		};

	};



	uart0_rts_cts: uart0-rts-cts {

		uart0-rts {

			  pins = "mfio57";

			  function = "uart0";

		};

		uart0-cts {

			  pins = "mfio58";

			  function = "uart0";

		};

	};

};



uart@... {

	...

	pinctrl-names = "default";

	pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;

	...

};



usb_vbus: fixed-regulator {

	...

	gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;

	...

};

Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt

+9 −9
Original line number Diff line number Diff line
@@ -17,10 +17,10 @@ mpp0 0 gpio, uart0(rxd) 
mpp1          1        gpo, uart0(txd)

mpp2          2        gpio, i2c0(sck), uart0(txd)

mpp3          3        gpio, i2c0(sda), uart0(rxd)

mpp4          4        gpio, cpu_pd(vdd)

mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)

mpp4          4        gpio, vdd(cpu-pd)

mpp5          5        gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk)

mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)

mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)

mpp7          7        gpo, ge0(txd1), tdm(dtx), audio(lrclk)

mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)

mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)

mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
@@ -52,8 +52,8 @@ mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) 
mpp31         31       gpio, tclk, ge0(txerr)

mpp32         32       gpio, spi0(cs0)

mpp33         33       gpio, dev(bootcs), spi0(cs0)

mpp34         34       gpo, dev(wen0), spi0(mosi)

mpp35         35       gpo, dev(oen), spi0(sck)

mpp34         34       gpo, dev(we0), spi0(mosi)

mpp35         35       gpo, dev(oe), spi0(sck)

mpp36         36       gpo, dev(a1), spi0(miso)

mpp37         37       gpo, dev(a0), sata0(prsnt)

mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
@@ -86,11 +86,11 @@ mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), 
mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),

                       uart0(rts)

mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)

mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),

mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout),

                       audio(sdi)

mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)

mpp61         61       gpo, dev(we1), uart1(txd), audio(lrclk)

mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),

                       audio(mclk), uart0(cts)

mpp63         63       gpo, spi0(sck), tclk

mpp64         64       gpio, spi0(miso), spi0-1(cs1)

mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
 
mpp64         64       gpio, spi0(miso), spi0(cs1)

mpp65         65       gpio, spi0(mosi), spi0(cs2)

Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt

+17 −17
Original line number Diff line number Diff line
@@ -15,24 +15,24 @@ name pins functions 
================================================================================

mpp0          0        gpio, dev(ad2), spi0(cs1), spi1(cs1)

mpp1          1        gpio, dev(ad3), spi0(mosi), spi1(mosi)

mpp2          2        gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)

mpp3          3        gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)

mpp2          2        gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi)

mpp3          3        gpio, dev(ad5), ptp(trig), led(p3), audio(mclk)

mpp4          4        gpio, dev(ad6), spi0(miso), spi1(miso)

mpp5          5        gpio, dev(ad7), spi0(cs2), spi1(cs2)

mpp6          6        gpio, dev(ad0), led(p1), audio(rclk)

mpp6          6        gpio, dev(ad0), led(p1), audio(lrclk)

mpp7          7        gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)

mpp8          8        gpio, dev (bootcs), spi0(cs0), spi1(cs0)

mpp9          9        gpio, nf(wen), spi0(sck), spi1(sck)

mpp10        10        gpio, nf(ren), dram(vttctrl), led(c1)

mpp9          9        gpio, spi0(sck), spi1(sck), nand(we)

mpp10        10        gpio, dram(vttctrl), led(c1), nand(re)

mpp11        11        gpio, dev(a0), led(c2), audio(sdo)

mpp12        12        gpio, dev(a1), audio(bclk)

mpp13        13        gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)

mpp13        13        gpio, dev(ready), pcie0(rstout), pcie1(rstout)

mpp14        14        gpio, i2c0(sda), uart1(txd)

mpp15        15        gpio, i2c0(sck), uart1(rxd)

mpp16        16        gpio, uart0(txd)

mpp17        17        gpio, uart0(rxd)

mpp18        18        gpio, tdm(intn)

mpp19        19        gpio, tdm(rstn)

mpp18        18        gpio, tdm(int)

mpp19        19        gpio, tdm(rst)

mpp20        20        gpio, tdm(pclk)

mpp21        21        gpio, tdm(fsync)

mpp22        22        gpio, tdm(drx)
@@ -45,12 +45,12 @@ mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) 
mpp29        29        gpio, pcie1(clkreq), ge1(rxclk), sd(d3)

mpp30        30        gpio, ge1(txd0), spi1(cs0)

mpp31        31        gpio, ge1(txd1), spi1(mosi)

mpp32        32        gpio, ge1(txd2), spi1(sck), ptp(triggen)

mpp32        32        gpio, ge1(txd2), spi1(sck), ptp(trig)

mpp33        33        gpio, ge1(txd3), spi1(miso)

mpp34        34        gpio, ge1(txclkout), spi1(sck)

mpp35        35        gpio, ge1(rxctl), spi1(cs1), spi0(cs2)

mpp36        36        gpio, pcie0(clkreq)

mpp37        37        gpio, pcie0(clkreq), tdm(intn), ge(mdc)

mpp37        37        gpio, pcie0(clkreq), tdm(int), ge(mdc)

mpp38        38        gpio, pcie1(clkreq), ge(mdio)

mpp39        39        gpio, ref(clkout)

mpp40        40        gpio, uart1(txd)
@@ -58,25 +58,25 @@ mpp41 41 gpio, uart1(rxd) 
mpp42        42        gpio, spi1(cs2), led(c0)

mpp43        43        gpio, sata0(prsnt), dram(vttctrl)

mpp44        44        gpio, sata0(prsnt)

mpp45        45        gpio, spi0(cs2), pcie0(rstoutn)

mpp46        46        gpio, led(p0), ge0(txd0), ge1(txd0)

mpp45        45        gpio, spi0(cs2), pcie0(rstout)

mpp46        46        gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1)

mpp47        47        gpio, led(p1), ge0(txd1), ge1(txd1)

mpp48        48        gpio, led(p2), ge0(txd2), ge1(txd2)

mpp49        49        gpio, led(p3), ge0(txd3), ge1(txd3)

mpp50        50        gpio, led(c0), ge0(rxd0), ge1(rxd0)

mpp51        51        gpio, led(c1), ge0(rxd1), ge1(rxd1)

mpp52        52        gpio, led(c2), ge0(rxd2), ge1(rxd2)

mpp53        53        gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)

mpp54        54        gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)

mpp53        53        gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3)

mpp54        54        gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl)

mpp55        55        gpio, ge0(rxclk), ge1(rxclk)

mpp56        56        gpio, ge0(txclkout), ge1(txclkout)

mpp57        57        gpio, ge0(txctl), ge1(txctl)

mpp57        57        gpio, ge0(txctl), ge1(txctl), dev(we0)

mpp58        58        gpio, led(c0)

mpp59        59        gpio, led(c1)

mpp60        60        gpio, uart1(txd), led(c2)

mpp61        61        gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)

mpp62        62        gpio, i2c1(sck), led(p1)

mpp63        63        gpio, ptp(triggen), led(p2)

mpp63        63        gpio, ptp(trig), led(p2), dev(burst/last)

mpp64        64        gpio, dram(vttctrl), led(p3)

mpp65        65        gpio, sata1(prsnt)

mpp66        66        gpio, ptp(eventreq), spi1(cs3)
 
mpp66        66        gpio, ptp(evreq), spi1(cs3)

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