Commit 939e7430 authored Jul 26, 2019 by Thierry Reding

arm64: tegra: Fix base address for SOR1 on Tegra194



The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.

Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 1aaa7698

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -1078,7 +1078,7 @@

		sor1: sor@15b40000 {
		compatible = "nvidia,tegra194-sor";
		reg = <0x155c0000 0x40000>;
		reg = <0x15b40000 0x40000>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
		<&bpmp TEGRA194_CLK_SOR1_OUT>,

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