Commit 937eea29 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-5.8-2020-04-24' of git://people.freedesktop.org/~agd5f/linux into drm-next 

amd-drm-next-5.8-2020-04-24:

amdgpu:
- Documentation improvements
- Enable FRU chip access on boards that support it
- RAS updates
- SR-IOV updates
- Powerplay locking fixes for older SMU versions
- VCN DPG (dynamic powergating) cleanup
- VCN 2.5 DPG enablement
- Rework GPU scheduler handling
- Improve scheduler priority handling
- Add SPM (streaming performance monitor) golden settings for navi
- GFX10 clockgating fixes
- DC ABM (automatic backlight modulation) fixes
- DC cursor and plane fixes
- DC watermark fixes
- DC clock handling fixes
- DC color management fixes
- GPU reset fixes
- Clean up MMIO access macros
- EEPROM access fixes
- Misc code cleanups

amdkfd:
- Misc code cleanups

radeon:
- Clean up safe reg list generation
- Misc code cleanups

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200424190827.4542-1-alexander.deucher@amd.com
parents 126a3406 e748f07d

Documentation/gpu/amdgpu.rst

+88 −0
Original line number Diff line number Diff line
@@ -202,3 +202,91 @@ busy_percent 


.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   :doc: busy_percent



GPU Product Information

=======================



Information about the GPU can be obtained on certain cards

via sysfs



product_name

------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: product_name



product_number

--------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: product_name



serial_number

-------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: serial_number



unique_id

---------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   :doc: unique_id



GPU Memory Usage Information

============================



Various memory accounting can be accessed via sysfs



mem_info_vram_total

-------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

   :doc: mem_info_vram_total



mem_info_vram_used

------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

   :doc: mem_info_vram_used



mem_info_vis_vram_total

-----------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

   :doc: mem_info_vis_vram_total



mem_info_vis_vram_used

----------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

   :doc: mem_info_vis_vram_used



mem_info_gtt_total

------------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c

   :doc: mem_info_gtt_total



mem_info_gtt_used

-----------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c

   :doc: mem_info_gtt_used



PCIe Accounting Information

===========================



pcie_bw

-------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   :doc: pcie_bw



pcie_replay_count

-----------------



.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   :doc: pcie_replay_count

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ 
	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \

	amdgpu_gmc.o amdgpu_mmhub.o amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \

	amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \

	amdgpu_umc.o smu_v11_0_i2c.o

	amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o



amdgpu-$(CONFIG_PERF_EVENTS) += amdgpu_pmu.o

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+41 −26
Original line number Diff line number Diff line
@@ -28,6 +28,18 @@ 
#ifndef __AMDGPU_H__

#define __AMDGPU_H__



#ifdef pr_fmt

#undef pr_fmt

#endif



#define pr_fmt(fmt) "amdgpu: " fmt



#ifdef dev_fmt

#undef dev_fmt

#endif



#define dev_fmt(fmt) "amdgpu: " fmt



#include "amdgpu_ctx.h"



#include <linux/atomic.h>
@@ -388,6 +400,13 @@ struct amdgpu_sa_bo { 
int amdgpu_fence_slab_init(void);

void amdgpu_fence_slab_fini(void);



enum amdgpu_ib_pool_type {

	AMDGPU_IB_POOL_NORMAL = 0,

	AMDGPU_IB_POOL_VM,

	AMDGPU_IB_POOL_DIRECT,



	AMDGPU_IB_POOL_MAX

};

/*

 * IRQS.

 */
@@ -439,7 +458,9 @@ struct amdgpu_fpriv { 
int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size, struct amdgpu_ib *ib);

		  unsigned size,

		  enum amdgpu_ib_pool_type pool,

		  struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct dma_fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
@@ -512,7 +533,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 
/*

 * Writeback

 */

#define AMDGPU_MAX_WB 128	/* Reserve at most 128 WB slots for amdgpu-owned rings. */

#define AMDGPU_MAX_WB 256	/* Reserve at most 256 WB slots for amdgpu-owned rings. */



struct amdgpu_wb {

	struct amdgpu_bo	*wb_obj;
@@ -843,7 +864,8 @@ struct amdgpu_device { 
	unsigned			num_rings;

	struct amdgpu_ring		*rings[AMDGPU_MAX_RINGS];

	bool				ib_pool_ready;

	struct amdgpu_sa_manager	ring_tmp_bo;

	struct amdgpu_sa_manager	ring_tmp_bo[AMDGPU_IB_POOL_MAX];

	struct amdgpu_sched		gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];



	/* interrupts */

	struct amdgpu_irq		irq;
@@ -935,9 +957,6 @@ struct amdgpu_device { 
	/* link all shadow bo */

	struct list_head                shadow_list;

	struct mutex                    shadow_list_lock;

	/* keep an lru list of rings by HW IP */

	struct list_head		ring_lru_list;

	spinlock_t			ring_lru_list_lock;



	/* record hw reset is performed */

	bool has_hw_reset;
@@ -946,8 +965,6 @@ struct amdgpu_device { 
	/* s3/s4 mask */

	bool                            in_suspend;



	/* record last mm index being written through WREG32*/

	unsigned long last_mm_index;

	bool                            in_gpu_reset;

	enum pp_mp1_state               mp1_state;

	struct mutex  lock_reset;
@@ -966,14 +983,17 @@ struct amdgpu_device { 
	uint64_t			unique_id;

	uint64_t	df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];



	/* device pstate */

	int				pstate;

	/* enable runtime pm on the device */

	bool                            runpm;

	bool                            in_runpm;



	bool                            pm_sysfs_en;

	bool                            ucode_sysfs_en;



	/* Chip product information */

	char				product_number[16];

	char				product_name[32];

	char				serial[16];

};



static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
@@ -990,9 +1010,9 @@ int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 


void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,

			       uint32_t *buf, size_t size, bool write);

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,

			    uint32_t acc_flags);

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

			uint32_t acc_flags);

void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    uint32_t acc_flags);
@@ -1010,25 +1030,20 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
/*

 * Registers read & write functions.

 */



#define AMDGPU_REGS_IDX       (1<<0)

#define AMDGPU_REGS_NO_KIQ    (1<<1)

#define AMDGPU_REGS_KIQ       (1<<2)



#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)

#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)



#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)

#define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ)

#define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))

#define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))



#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))

#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))



#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)

#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)

#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)

#define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
@@ -1065,7 +1080,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
		tmp_ |= ((val) & ~(mask));			\

		WREG32_PLL(reg, tmp_);				\

	} while (0)

#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))

#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))

#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))

#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

+3 −0
Original line number Diff line number Diff line
@@ -543,6 +543,9 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 
	uint32_t temp;

	struct v10_compute_mqd *m = get_mqd(mqd);



	if (adev->in_gpu_reset)

		return -EIO;



#if 0

	unsigned long flags;

	int retry;

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

+19 −21
Original line number Diff line number Diff line
@@ -362,13 +362,13 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) 
	ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate,

					&param);

	if (ret) {

		pr_err("amdgpu: failed to validate PT BOs\n");

		pr_err("failed to validate PT BOs\n");

		return ret;

	}



	ret = amdgpu_amdkfd_validate(&param, pd);

	if (ret) {

		pr_err("amdgpu: failed to validate PD\n");

		pr_err("failed to validate PD\n");

		return ret;

	}
@@ -377,7 +377,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) 
	if (vm->use_cpu_for_update) {

		ret = amdgpu_bo_kmap(pd, NULL);

		if (ret) {

			pr_err("amdgpu: failed to kmap PD, ret=%d\n", ret);

			pr_err("failed to kmap PD, ret=%d\n", ret);

			return ret;

		}

	}
@@ -660,15 +660,15 @@ static int reserve_bo_and_vm(struct kgd_mem *mem, 


	ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,

				     false, &ctx->duplicates);

	if (!ret)

		ctx->reserved = true;

	else {

		pr_err("Failed to reserve buffers in ttm\n");

	if (ret) {

		pr_err("Failed to reserve buffers in ttm.\n");

		kfree(ctx->vm_pd);

		ctx->vm_pd = NULL;

		return ret;

	}



	return ret;

	ctx->reserved = true;

	return 0;

}



/**
@@ -733,17 +733,15 @@ static int reserve_bo_and_cond_vms(struct kgd_mem *mem, 


	ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list,

				     false, &ctx->duplicates);

	if (!ret)

		ctx->reserved = true;

	else

		pr_err("Failed to reserve buffers in ttm.\n");



	if (ret) {

		pr_err("Failed to reserve buffers in ttm.\n");

		kfree(ctx->vm_pd);

		ctx->vm_pd = NULL;

		return ret;

	}



	return ret;

	ctx->reserved = true;

	return 0;

}



/**
@@ -1286,22 +1284,22 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 
	struct kfd_bo_va_list *entry, *tmp;

	struct bo_vm_reservation_context ctx;

	struct ttm_validate_buffer *bo_list_entry;

	unsigned int mapped_to_gpu_memory;

	int ret;



	mutex_lock(&mem->lock);

	mapped_to_gpu_memory = mem->mapped_to_gpu_memory;

	mutex_unlock(&mem->lock);

	/* lock is not needed after this, since mem is unused and will

	 * be freed anyway

	 */



	if (mem->mapped_to_gpu_memory > 0) {

	if (mapped_to_gpu_memory > 0) {

		pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n",

				mem->va, bo_size);

		mutex_unlock(&mem->lock);

		return -EBUSY;

	}



	mutex_unlock(&mem->lock);

	/* lock is not needed after this, since mem is unused and will

	 * be freed anyway

	 */



	/* No more MMU notifiers */

	amdgpu_mn_unregister(mem->bo);

CRA Git | Maintained and supported by SUSTech CRA and CCSE